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      1 /****************************************************************************
      2  ****************************************************************************
      3  ***
      4  ***   This header was automatically generated from a Linux kernel header
      5  ***   of the same name, to make information necessary for userspace to
      6  ***   call into the kernel available to libc.  It contains only constants,
      7  ***   structures, and macros generated from the original header, and thus,
      8  ***   contains no copyrightable information.
      9  ***
     10  ****************************************************************************
     11  ****************************************************************************/
     12 #ifndef _ASM_DMA_H
     13 #define _ASM_DMA_H
     14 
     15 #include <linux/spinlock.h>
     16 #include <asm/io.h>
     17 #include <linux/delay.h>
     18 
     19 #ifdef HAVE_REALLY_SLOW_DMA_CONTROLLER
     20 #define dma_outb outb_p
     21 #else
     22 #define dma_outb outb
     23 #endif
     24 
     25 #define dma_inb inb
     26 
     27 #define MAX_DMA_CHANNELS 8
     28 
     29 #define MAX_DMA_ADDRESS (PAGE_OFFSET+0x1000000)
     30 
     31 #define IO_DMA1_BASE 0x00
     32 #define IO_DMA2_BASE 0xC0
     33 
     34 #define DMA1_CMD_REG 0x08
     35 #define DMA1_STAT_REG 0x08
     36 #define DMA1_REQ_REG 0x09
     37 #define DMA1_MASK_REG 0x0A
     38 #define DMA1_MODE_REG 0x0B
     39 #define DMA1_CLEAR_FF_REG 0x0C
     40 #define DMA1_TEMP_REG 0x0D
     41 #define DMA1_RESET_REG 0x0D
     42 #define DMA1_CLR_MASK_REG 0x0E
     43 #define DMA1_MASK_ALL_REG 0x0F
     44 
     45 #define DMA2_CMD_REG 0xD0
     46 #define DMA2_STAT_REG 0xD0
     47 #define DMA2_REQ_REG 0xD2
     48 #define DMA2_MASK_REG 0xD4
     49 #define DMA2_MODE_REG 0xD6
     50 #define DMA2_CLEAR_FF_REG 0xD8
     51 #define DMA2_TEMP_REG 0xDA
     52 #define DMA2_RESET_REG 0xDA
     53 #define DMA2_CLR_MASK_REG 0xDC
     54 #define DMA2_MASK_ALL_REG 0xDE
     55 
     56 #define DMA_ADDR_0 0x00
     57 #define DMA_ADDR_1 0x02
     58 #define DMA_ADDR_2 0x04
     59 #define DMA_ADDR_3 0x06
     60 #define DMA_ADDR_4 0xC0
     61 #define DMA_ADDR_5 0xC4
     62 #define DMA_ADDR_6 0xC8
     63 #define DMA_ADDR_7 0xCC
     64 
     65 #define DMA_CNT_0 0x01
     66 #define DMA_CNT_1 0x03
     67 #define DMA_CNT_2 0x05
     68 #define DMA_CNT_3 0x07
     69 #define DMA_CNT_4 0xC2
     70 #define DMA_CNT_5 0xC6
     71 #define DMA_CNT_6 0xCA
     72 #define DMA_CNT_7 0xCE
     73 
     74 #define DMA_PAGE_0 0x87
     75 #define DMA_PAGE_1 0x83
     76 #define DMA_PAGE_2 0x81
     77 #define DMA_PAGE_3 0x82
     78 #define DMA_PAGE_5 0x8B
     79 #define DMA_PAGE_6 0x89
     80 #define DMA_PAGE_7 0x8A
     81 
     82 #define DMA_MODE_READ 0x44
     83 #define DMA_MODE_WRITE 0x48
     84 #define DMA_MODE_CASCADE 0xC0
     85 
     86 #define DMA_AUTOINIT 0x10
     87 
     88 #define isa_dma_bridge_buggy (0)
     89 
     90 #endif
     91