1 /**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 **************************************************************************** 11 ****************************************************************************/ 12 #ifndef _LINUX_SPI_CPCAP_H 13 #define _LINUX_SPI_CPCAP_H 14 15 #include <linux/ioctl.h> 16 17 #define CPCAP_DEV_NAME "cpcap" 18 #define CPCAP_NUM_REG_CPCAP (CPCAP_REG_END - CPCAP_REG_START + 1) 19 20 #define CPCAP_IRQ_INT1_INDEX 0 21 #define CPCAP_IRQ_INT2_INDEX 16 22 #define CPCAP_IRQ_INT3_INDEX 32 23 #define CPCAP_IRQ_INT4_INDEX 48 24 #define CPCAP_IRQ_INT5_INDEX 64 25 26 #define CPCAP_HWCFG_NUM 2 27 28 #define CPCAP_HWCFG0_SEC_STBY_SW1 0x0001 29 #define CPCAP_HWCFG0_SEC_STBY_SW2 0x0002 30 #define CPCAP_HWCFG0_SEC_STBY_SW3 0x0004 31 #define CPCAP_HWCFG0_SEC_STBY_SW4 0x0008 32 #define CPCAP_HWCFG0_SEC_STBY_SW5 0x0010 33 #define CPCAP_HWCFG0_SEC_STBY_VAUDIO 0x0020 34 #define CPCAP_HWCFG0_SEC_STBY_VCAM 0x0040 35 #define CPCAP_HWCFG0_SEC_STBY_VCSI 0x0080 36 #define CPCAP_HWCFG0_SEC_STBY_VDAC 0x0100 37 #define CPCAP_HWCFG0_SEC_STBY_VDIG 0x0200 38 #define CPCAP_HWCFG0_SEC_STBY_VHVIO 0x0400 39 #define CPCAP_HWCFG0_SEC_STBY_VPLL 0x0800 40 #define CPCAP_HWCFG0_SEC_STBY_VRF1 0x1000 41 #define CPCAP_HWCFG0_SEC_STBY_VRF2 0x2000 42 #define CPCAP_HWCFG0_SEC_STBY_VRFREF 0x4000 43 #define CPCAP_HWCFG0_SEC_STBY_VSDIO 0x8000 44 45 #define CPCAP_HWCFG1_SEC_STBY_VWLAN1 0x0001 46 #define CPCAP_HWCFG1_SEC_STBY_VWLAN2 0x0002 47 #define CPCAP_HWCFG1_SEC_STBY_VSIM 0x0004 48 #define CPCAP_HWCFG1_SEC_STBY_VSIMCARD 0x0008 49 50 #define CPCAP_WHISPER_MODE_PU 0x00000001 51 #define CPCAP_WHISPER_ENABLE_UART 0x00000002 52 #define CPCAP_WHISPER_ACCY_MASK 0xF8000000 53 #define CPCAP_WHISPER_ACCY_SHFT 27 54 #define CPCAP_WHISPER_ID_SIZE 16 55 #define CPCAP_WHISPER_PROP_SIZE 7 56 57 enum cpcap_regulator_id { 58 CPCAP_SW2, 59 CPCAP_SW4, 60 CPCAP_SW5, 61 CPCAP_VCAM, 62 CPCAP_VCSI, 63 CPCAP_VDAC, 64 CPCAP_VDIG, 65 CPCAP_VFUSE, 66 CPCAP_VHVIO, 67 CPCAP_VSDIO, 68 CPCAP_VPLL, 69 CPCAP_VRF1, 70 CPCAP_VRF2, 71 CPCAP_VRFREF, 72 CPCAP_VWLAN1, 73 CPCAP_VWLAN2, 74 CPCAP_VSIM, 75 CPCAP_VSIMCARD, 76 CPCAP_VVIB, 77 CPCAP_VUSB, 78 CPCAP_VAUDIO, 79 CPCAP_NUM_REGULATORS 80 }; 81 82 enum cpcap_reg { 83 CPCAP_REG_START, 84 85 CPCAP_REG_INT1 = CPCAP_REG_START, 86 CPCAP_REG_INT2, 87 CPCAP_REG_INT3, 88 CPCAP_REG_INT4, 89 CPCAP_REG_INTM1, 90 CPCAP_REG_INTM2, 91 CPCAP_REG_INTM3, 92 CPCAP_REG_INTM4, 93 CPCAP_REG_INTS1, 94 CPCAP_REG_INTS2, 95 CPCAP_REG_INTS3, 96 CPCAP_REG_INTS4, 97 CPCAP_REG_ASSIGN1, 98 CPCAP_REG_ASSIGN2, 99 CPCAP_REG_ASSIGN3, 100 CPCAP_REG_ASSIGN4, 101 CPCAP_REG_ASSIGN5, 102 CPCAP_REG_ASSIGN6, 103 CPCAP_REG_VERSC1, 104 CPCAP_REG_VERSC2, 105 106 CPCAP_REG_MI1, 107 CPCAP_REG_MIM1, 108 CPCAP_REG_MI2, 109 CPCAP_REG_MIM2, 110 CPCAP_REG_UCC1, 111 CPCAP_REG_UCC2, 112 CPCAP_REG_PC1, 113 CPCAP_REG_PC2, 114 CPCAP_REG_BPEOL, 115 CPCAP_REG_PGC, 116 CPCAP_REG_MT1, 117 CPCAP_REG_MT2, 118 CPCAP_REG_MT3, 119 CPCAP_REG_PF, 120 121 CPCAP_REG_SCC, 122 CPCAP_REG_SW1, 123 CPCAP_REG_SW2, 124 CPCAP_REG_UCTM, 125 CPCAP_REG_TOD1, 126 CPCAP_REG_TOD2, 127 CPCAP_REG_TODA1, 128 CPCAP_REG_TODA2, 129 CPCAP_REG_DAY, 130 CPCAP_REG_DAYA, 131 CPCAP_REG_VAL1, 132 CPCAP_REG_VAL2, 133 134 CPCAP_REG_SDVSPLL, 135 CPCAP_REG_SI2CC1, 136 CPCAP_REG_Si2CC2, 137 CPCAP_REG_S1C1, 138 CPCAP_REG_S1C2, 139 CPCAP_REG_S2C1, 140 CPCAP_REG_S2C2, 141 CPCAP_REG_S3C, 142 CPCAP_REG_S4C1, 143 CPCAP_REG_S4C2, 144 CPCAP_REG_S5C, 145 CPCAP_REG_S6C, 146 CPCAP_REG_VCAMC, 147 CPCAP_REG_VCSIC, 148 CPCAP_REG_VDACC, 149 CPCAP_REG_VDIGC, 150 CPCAP_REG_VFUSEC, 151 CPCAP_REG_VHVIOC, 152 CPCAP_REG_VSDIOC, 153 CPCAP_REG_VPLLC, 154 CPCAP_REG_VRF1C, 155 CPCAP_REG_VRF2C, 156 CPCAP_REG_VRFREFC, 157 CPCAP_REG_VWLAN1C, 158 CPCAP_REG_VWLAN2C, 159 CPCAP_REG_VSIMC, 160 CPCAP_REG_VVIBC, 161 CPCAP_REG_VUSBC, 162 CPCAP_REG_VUSBINT1C, 163 CPCAP_REG_VUSBINT2C, 164 CPCAP_REG_URT, 165 CPCAP_REG_URM1, 166 CPCAP_REG_URM2, 167 168 CPCAP_REG_VAUDIOC, 169 CPCAP_REG_CC, 170 CPCAP_REG_CDI, 171 CPCAP_REG_SDAC, 172 CPCAP_REG_SDACDI, 173 CPCAP_REG_TXI, 174 CPCAP_REG_TXMP, 175 CPCAP_REG_RXOA, 176 CPCAP_REG_RXVC, 177 CPCAP_REG_RXCOA, 178 CPCAP_REG_RXSDOA, 179 CPCAP_REG_RXEPOA, 180 CPCAP_REG_RXLL, 181 CPCAP_REG_A2LA, 182 CPCAP_REG_MIPIS1, 183 CPCAP_REG_MIPIS2, 184 CPCAP_REG_MIPIS3, 185 CPCAP_REG_LVAB, 186 187 CPCAP_REG_CCC1, 188 CPCAP_REG_CRM, 189 CPCAP_REG_CCCC2, 190 CPCAP_REG_CCS1, 191 CPCAP_REG_CCS2, 192 CPCAP_REG_CCA1, 193 CPCAP_REG_CCA2, 194 CPCAP_REG_CCM, 195 CPCAP_REG_CCO, 196 CPCAP_REG_CCI, 197 198 CPCAP_REG_ADCC1, 199 CPCAP_REG_ADCC2, 200 CPCAP_REG_ADCD0, 201 CPCAP_REG_ADCD1, 202 CPCAP_REG_ADCD2, 203 CPCAP_REG_ADCD3, 204 CPCAP_REG_ADCD4, 205 CPCAP_REG_ADCD5, 206 CPCAP_REG_ADCD6, 207 CPCAP_REG_ADCD7, 208 CPCAP_REG_ADCAL1, 209 CPCAP_REG_ADCAL2, 210 211 CPCAP_REG_USBC1, 212 CPCAP_REG_USBC2, 213 CPCAP_REG_USBC3, 214 CPCAP_REG_UVIDL, 215 CPCAP_REG_UVIDH, 216 CPCAP_REG_UPIDL, 217 CPCAP_REG_UPIDH, 218 CPCAP_REG_UFC1, 219 CPCAP_REG_UFC2, 220 CPCAP_REG_UFC3, 221 CPCAP_REG_UIC1, 222 CPCAP_REG_UIC2, 223 CPCAP_REG_UIC3, 224 CPCAP_REG_USBOTG1, 225 CPCAP_REG_USBOTG2, 226 CPCAP_REG_USBOTG3, 227 CPCAP_REG_UIER1, 228 CPCAP_REG_UIER2, 229 CPCAP_REG_UIER3, 230 CPCAP_REG_UIEF1, 231 CPCAP_REG_UIEF2, 232 CPCAP_REG_UIEF3, 233 CPCAP_REG_UIS, 234 CPCAP_REG_UIL, 235 CPCAP_REG_USBD, 236 CPCAP_REG_SCR1, 237 CPCAP_REG_SCR2, 238 CPCAP_REG_SCR3, 239 CPCAP_REG_VMC, 240 CPCAP_REG_OWDC, 241 CPCAP_REG_GPIO0, 242 CPCAP_REG_GPIO1, 243 CPCAP_REG_GPIO2, 244 CPCAP_REG_GPIO3, 245 CPCAP_REG_GPIO4, 246 CPCAP_REG_GPIO5, 247 CPCAP_REG_GPIO6, 248 249 CPCAP_REG_MDLC, 250 CPCAP_REG_KLC, 251 CPCAP_REG_ADLC, 252 CPCAP_REG_REDC, 253 CPCAP_REG_GREENC, 254 CPCAP_REG_BLUEC, 255 CPCAP_REG_CFC, 256 CPCAP_REG_ABC, 257 CPCAP_REG_BLEDC, 258 CPCAP_REG_CLEDC, 259 260 CPCAP_REG_OW1C, 261 CPCAP_REG_OW1D, 262 CPCAP_REG_OW1I, 263 CPCAP_REG_OW1IE, 264 CPCAP_REG_OW1, 265 CPCAP_REG_OW2C, 266 CPCAP_REG_OW2D, 267 CPCAP_REG_OW2I, 268 CPCAP_REG_OW2IE, 269 CPCAP_REG_OW2, 270 CPCAP_REG_OW3C, 271 CPCAP_REG_OW3D, 272 CPCAP_REG_OW3I, 273 CPCAP_REG_OW3IE, 274 CPCAP_REG_OW3, 275 CPCAP_REG_GCAIC, 276 CPCAP_REG_GCAIM, 277 CPCAP_REG_LGDIR, 278 CPCAP_REG_LGPU, 279 CPCAP_REG_LGPIN, 280 CPCAP_REG_LGMASK, 281 CPCAP_REG_LDEB, 282 CPCAP_REG_LGDET, 283 CPCAP_REG_LMISC, 284 CPCAP_REG_LMACE, 285 286 CPCAP_REG_END = CPCAP_REG_LMACE, 287 288 CPCAP_REG_MAX 289 = CPCAP_REG_END, 290 291 CPCAP_REG_SIZE = CPCAP_REG_MAX + 1, 292 CPCAP_REG_UNUSED = CPCAP_REG_MAX + 2, 293 }; 294 295 enum { 296 CPCAP_IOCTL_NUM_TEST__START, 297 CPCAP_IOCTL_NUM_TEST_READ_REG, 298 CPCAP_IOCTL_NUM_TEST_WRITE_REG, 299 CPCAP_IOCTL_NUM_TEST__END, 300 301 CPCAP_IOCTL_NUM_ADC__START, 302 CPCAP_IOCTL_NUM_ADC_PHASE, 303 CPCAP_IOCTL_NUM_ADC__END, 304 305 CPCAP_IOCTL_NUM_BATT__START, 306 CPCAP_IOCTL_NUM_BATT_DISPLAY_UPDATE, 307 CPCAP_IOCTL_NUM_BATT_ATOD_ASYNC, 308 CPCAP_IOCTL_NUM_BATT_ATOD_SYNC, 309 CPCAP_IOCTL_NUM_BATT_ATOD_READ, 310 CPCAP_IOCTL_NUM_BATT__END, 311 312 CPCAP_IOCTL_NUM_UC__START, 313 CPCAP_IOCTL_NUM_UC_MACRO_START, 314 CPCAP_IOCTL_NUM_UC_MACRO_STOP, 315 CPCAP_IOCTL_NUM_UC_GET_VENDOR, 316 CPCAP_IOCTL_NUM_UC_SET_TURBO_MODE, 317 CPCAP_IOCTL_NUM_UC__END, 318 319 CPCAP_IOCTL_NUM_ACCY__START, 320 CPCAP_IOCTL_NUM_ACCY_WHISPER, 321 CPCAP_IOCTL_NUM_ACCY__END, 322 }; 323 324 enum cpcap_irqs { 325 CPCAP_IRQ__START, 326 CPCAP_IRQ_HSCLK = CPCAP_IRQ_INT1_INDEX, 327 CPCAP_IRQ_PRIMAC, 328 CPCAP_IRQ_SECMAC, 329 CPCAP_IRQ_LOWBPL, 330 CPCAP_IRQ_SEC2PRI, 331 CPCAP_IRQ_LOWBPH, 332 CPCAP_IRQ_EOL, 333 CPCAP_IRQ_TS, 334 CPCAP_IRQ_ADCDONE, 335 CPCAP_IRQ_HS, 336 CPCAP_IRQ_MB2, 337 CPCAP_IRQ_VBUSOV, 338 CPCAP_IRQ_RVRS_CHRG, 339 CPCAP_IRQ_CHRG_DET, 340 CPCAP_IRQ_IDFLOAT, 341 CPCAP_IRQ_IDGND, 342 343 CPCAP_IRQ_SE1 = CPCAP_IRQ_INT2_INDEX, 344 CPCAP_IRQ_SESSEND, 345 CPCAP_IRQ_SESSVLD, 346 CPCAP_IRQ_VBUSVLD, 347 CPCAP_IRQ_CHRG_CURR1, 348 CPCAP_IRQ_CHRG_CURR2, 349 CPCAP_IRQ_RVRS_MODE, 350 CPCAP_IRQ_ON, 351 CPCAP_IRQ_ON2, 352 CPCAP_IRQ_CLK, 353 CPCAP_IRQ_1HZ, 354 CPCAP_IRQ_PTT, 355 CPCAP_IRQ_SE0CONN, 356 CPCAP_IRQ_CHRG_SE1B, 357 CPCAP_IRQ_UART_ECHO_OVERRUN, 358 CPCAP_IRQ_EXTMEMHD, 359 360 CPCAP_IRQ_WARM = CPCAP_IRQ_INT3_INDEX, 361 CPCAP_IRQ_SYSRSTR, 362 CPCAP_IRQ_SOFTRST, 363 CPCAP_IRQ_DIEPWRDWN, 364 CPCAP_IRQ_DIETEMPH, 365 CPCAP_IRQ_PC, 366 CPCAP_IRQ_OFLOWSW, 367 CPCAP_IRQ_TODA, 368 CPCAP_IRQ_OPT_SEL_DTCH, 369 CPCAP_IRQ_OPT_SEL_STATE, 370 CPCAP_IRQ_ONEWIRE1, 371 CPCAP_IRQ_ONEWIRE2, 372 CPCAP_IRQ_ONEWIRE3, 373 CPCAP_IRQ_UCRESET, 374 CPCAP_IRQ_PWRGOOD, 375 CPCAP_IRQ_USBDPLLCLK, 376 377 CPCAP_IRQ_DPI = CPCAP_IRQ_INT4_INDEX, 378 CPCAP_IRQ_DMI, 379 CPCAP_IRQ_UCBUSY, 380 CPCAP_IRQ_GCAI_CURR1, 381 CPCAP_IRQ_GCAI_CURR2, 382 CPCAP_IRQ_SB_MAX_RETRANSMIT_ERR, 383 CPCAP_IRQ_BATTDETB, 384 CPCAP_IRQ_PRIHALT, 385 CPCAP_IRQ_SECHALT, 386 CPCAP_IRQ_CC_CAL, 387 388 CPCAP_IRQ_UC_PRIROMR = CPCAP_IRQ_INT5_INDEX, 389 CPCAP_IRQ_UC_PRIRAMW, 390 CPCAP_IRQ_UC_PRIRAMR, 391 CPCAP_IRQ_UC_USEROFF, 392 CPCAP_IRQ_UC_PRIMACRO_4, 393 CPCAP_IRQ_UC_PRIMACRO_5, 394 CPCAP_IRQ_UC_PRIMACRO_6, 395 CPCAP_IRQ_UC_PRIMACRO_7, 396 CPCAP_IRQ_UC_PRIMACRO_8, 397 CPCAP_IRQ_UC_PRIMACRO_9, 398 CPCAP_IRQ_UC_PRIMACRO_10, 399 CPCAP_IRQ_UC_PRIMACRO_11, 400 CPCAP_IRQ_UC_PRIMACRO_12, 401 CPCAP_IRQ_UC_PRIMACRO_13, 402 CPCAP_IRQ_UC_PRIMACRO_14, 403 CPCAP_IRQ_UC_PRIMACRO_15, 404 CPCAP_IRQ__NUM 405 }; 406 407 enum cpcap_adc_bank0 { 408 CPCAP_ADC_AD0_BATTDETB, 409 CPCAP_ADC_BATTP, 410 CPCAP_ADC_VBUS, 411 CPCAP_ADC_AD3, 412 CPCAP_ADC_BPLUS_AD4, 413 CPCAP_ADC_CHG_ISENSE, 414 CPCAP_ADC_BATTI_ADC, 415 CPCAP_ADC_USB_ID, 416 417 CPCAP_ADC_BANK0_NUM, 418 }; 419 420 enum cpcap_adc_bank1 { 421 CPCAP_ADC_AD8, 422 CPCAP_ADC_AD9, 423 CPCAP_ADC_LICELL, 424 CPCAP_ADC_HV_BATTP, 425 CPCAP_ADC_TSX1_AD12, 426 CPCAP_ADC_TSX2_AD13, 427 CPCAP_ADC_TSY1_AD14, 428 CPCAP_ADC_TSY2_AD15, 429 430 CPCAP_ADC_BANK1_NUM, 431 }; 432 433 enum cpcap_adc_format { 434 CPCAP_ADC_FORMAT_RAW, 435 CPCAP_ADC_FORMAT_PHASED, 436 CPCAP_ADC_FORMAT_CONVERTED, 437 }; 438 439 enum cpcap_adc_timing { 440 CPCAP_ADC_TIMING_IMM, 441 CPCAP_ADC_TIMING_IN, 442 CPCAP_ADC_TIMING_OUT, 443 }; 444 445 enum cpcap_adc_type { 446 CPCAP_ADC_TYPE_BANK_0, 447 CPCAP_ADC_TYPE_BANK_1, 448 CPCAP_ADC_TYPE_BATT_PI, 449 }; 450 451 enum cpcap_macro { 452 CPCAP_MACRO_ROMR, 453 CPCAP_MACRO_RAMW, 454 CPCAP_MACRO_RAMR, 455 CPCAP_MACRO_USEROFF, 456 CPCAP_MACRO_4, 457 CPCAP_MACRO_5, 458 CPCAP_MACRO_6, 459 CPCAP_MACRO_7, 460 CPCAP_MACRO_8, 461 CPCAP_MACRO_9, 462 CPCAP_MACRO_10, 463 CPCAP_MACRO_11, 464 CPCAP_MACRO_12, 465 CPCAP_MACRO_13, 466 CPCAP_MACRO_14, 467 CPCAP_MACRO_15, 468 469 CPCAP_MACRO__END, 470 }; 471 472 enum cpcap_vendor { 473 CPCAP_VENDOR_ST, 474 CPCAP_VENDOR_TI, 475 }; 476 477 enum cpcap_revision { 478 CPCAP_REVISION_1_0 = 0x08, 479 CPCAP_REVISION_1_1 = 0x09, 480 CPCAP_REVISION_2_0 = 0x10, 481 CPCAP_REVISION_2_1 = 0x11, 482 }; 483 484 enum cpcap_batt_usb_model { 485 CPCAP_BATT_USB_MODEL_NONE, 486 CPCAP_BATT_USB_MODEL_USB, 487 CPCAP_BATT_USB_MODEL_FACTORY, 488 }; 489 490 struct cpcap_spi_init_data { 491 enum cpcap_reg reg; 492 unsigned short data; 493 }; 494 495 struct cpcap_adc_ato { 496 unsigned short ato_in; 497 unsigned short atox_in; 498 unsigned short adc_ps_factor_in; 499 unsigned short atox_ps_factor_in; 500 unsigned short ato_out; 501 unsigned short atox_out; 502 unsigned short adc_ps_factor_out; 503 unsigned short atox_ps_factor_out; 504 }; 505 506 struct cpcap_batt_data { 507 int status; 508 int health; 509 int present; 510 int capacity; 511 int batt_volt; 512 int batt_temp; 513 }; 514 515 struct cpcap_batt_ac_data { 516 int online; 517 }; 518 519 struct cpcap_batt_usb_data { 520 int online; 521 int current_now; 522 enum cpcap_batt_usb_model model; 523 }; 524 525 struct cpcap_device; 526 527 struct cpcap_adc_us_request { 528 enum cpcap_adc_format format; 529 enum cpcap_adc_timing timing; 530 enum cpcap_adc_type type; 531 int status; 532 int result[CPCAP_ADC_BANK0_NUM]; 533 }; 534 535 struct cpcap_adc_phase { 536 signed char offset_batti; 537 unsigned char slope_batti; 538 signed char offset_chrgi; 539 unsigned char slope_chrgi; 540 signed char offset_battp; 541 unsigned char slope_battp; 542 signed char offset_bp; 543 unsigned char slope_bp; 544 signed char offset_battt; 545 unsigned char slope_battt; 546 signed char offset_chrgv; 547 unsigned char slope_chrgv; 548 }; 549 550 struct cpcap_regacc { 551 unsigned short reg; 552 unsigned short value; 553 unsigned short mask; 554 }; 555 556 struct cpcap_whisper_request { 557 unsigned int cmd; 558 char dock_id[CPCAP_WHISPER_ID_SIZE]; 559 char dock_prop[CPCAP_WHISPER_PROP_SIZE]; 560 }; 561 562 #define CPCAP_IOCTL_TEST_READ_REG _IOWR(0, CPCAP_IOCTL_NUM_TEST_READ_REG, struct cpcap_regacc*) 563 564 #define CPCAP_IOCTL_TEST_WRITE_REG _IOWR(0, CPCAP_IOCTL_NUM_TEST_WRITE_REG, struct cpcap_regacc*) 565 566 #define CPCAP_IOCTL_ADC_PHASE _IOWR(0, CPCAP_IOCTL_NUM_ADC_PHASE, struct cpcap_adc_phase*) 567 568 #define CPCAP_IOCTL_BATT_DISPLAY_UPDATE _IOW(0, CPCAP_IOCTL_NUM_BATT_DISPLAY_UPDATE, struct cpcap_batt_data*) 569 570 #define CPCAP_IOCTL_BATT_ATOD_ASYNC _IOW(0, CPCAP_IOCTL_NUM_BATT_ATOD_ASYNC, struct cpcap_adc_us_request*) 571 572 #define CPCAP_IOCTL_BATT_ATOD_SYNC _IOWR(0, CPCAP_IOCTL_NUM_BATT_ATOD_SYNC, struct cpcap_adc_us_request*) 573 574 #define CPCAP_IOCTL_BATT_ATOD_READ _IOWR(0, CPCAP_IOCTL_NUM_BATT_ATOD_READ, struct cpcap_adc_us_request*) 575 576 #define CPCAP_IOCTL_UC_MACRO_START _IOWR(0, CPCAP_IOCTL_NUM_UC_MACRO_START, enum cpcap_macro) 577 578 #define CPCAP_IOCTL_UC_MACRO_STOP _IOWR(0, CPCAP_IOCTL_NUM_UC_MACRO_STOP, enum cpcap_macro) 579 580 #define CPCAP_IOCTL_UC_GET_VENDOR _IOWR(0, CPCAP_IOCTL_NUM_UC_GET_VENDOR, enum cpcap_vendor) 581 582 #define CPCAP_IOCTL_UC_SET_TURBO_MODE _IOW(0, CPCAP_IOCTL_NUM_UC_SET_TURBO_MODE, unsigned short) 583 584 #define CPCAP_IOCTL_ACCY_WHISPER _IOW(0, CPCAP_IOCTL_NUM_ACCY_WHISPER, struct cpcap_whisper_request*) 585 586 #endif 587 588
