1 /* $Id: dma.h,v 1.7 1992/12/14 00:29:34 root Exp root $ 2 * linux/include/asm/dma.h: Defines for using and allocating dma channels. 3 * Written by Hennus Bergman, 1992. 4 * High DMA channel support & info by Hannu Savolainen 5 * and John Boyd, Nov. 1992. 6 */ 7 8 #ifndef _ASM_DMA_H 9 #define _ASM_DMA_H 10 11 #include <linux/spinlock.h> /* And spinlocks */ 12 #include <asm/io.h> /* need byte IO */ 13 #include <linux/delay.h> 14 15 16 #ifdef HAVE_REALLY_SLOW_DMA_CONTROLLER 17 #define dma_outb outb_p 18 #else 19 #define dma_outb outb 20 #endif 21 22 #define dma_inb inb 23 24 /* 25 * NOTES about DMA transfers: 26 * 27 * controller 1: channels 0-3, byte operations, ports 00-1F 28 * controller 2: channels 4-7, word operations, ports C0-DF 29 * 30 * - ALL registers are 8 bits only, regardless of transfer size 31 * - channel 4 is not used - cascades 1 into 2. 32 * - channels 0-3 are byte - addresses/counts are for physical bytes 33 * - channels 5-7 are word - addresses/counts are for physical words 34 * - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries 35 * - transfer count loaded to registers is 1 less than actual count 36 * - controller 2 offsets are all even (2x offsets for controller 1) 37 * - page registers for 5-7 don't use data bit 0, represent 128K pages 38 * - page registers for 0-3 use bit 0, represent 64K pages 39 * 40 * DMA transfers are limited to the lower 16MB of _physical_ memory. 41 * Note that addresses loaded into registers must be _physical_ addresses, 42 * not logical addresses (which may differ if paging is active). 43 * 44 * Address mapping for channels 0-3: 45 * 46 * A23 ... A16 A15 ... A8 A7 ... A0 (Physical addresses) 47 * | ... | | ... | | ... | 48 * | ... | | ... | | ... | 49 * | ... | | ... | | ... | 50 * P7 ... P0 A7 ... A0 A7 ... A0 51 * | Page | Addr MSB | Addr LSB | (DMA registers) 52 * 53 * Address mapping for channels 5-7: 54 * 55 * A23 ... A17 A16 A15 ... A9 A8 A7 ... A1 A0 (Physical addresses) 56 * | ... | \ \ ... \ \ \ ... \ \ 57 * | ... | \ \ ... \ \ \ ... \ (not used) 58 * | ... | \ \ ... \ \ \ ... \ 59 * P7 ... P1 (0) A7 A6 ... A0 A7 A6 ... A0 60 * | Page | Addr MSB | Addr LSB | (DMA registers) 61 * 62 * Again, channels 5-7 transfer _physical_ words (16 bits), so addresses 63 * and counts _must_ be word-aligned (the lowest address bit is _ignored_ at 64 * the hardware level, so odd-byte transfers aren't possible). 65 * 66 * Transfer count (_not # bytes_) is limited to 64K, represented as actual 67 * count - 1 : 64K => 0xFFFF, 1 => 0x0000. Thus, count is always 1 or more, 68 * and up to 128K bytes may be transferred on channels 5-7 in one operation. 69 * 70 */ 71 72 #define MAX_DMA_CHANNELS 8 73 74 /* The maximum address that we can perform a DMA transfer to on this platform */ 75 #define MAX_DMA_ADDRESS (PAGE_OFFSET+0x1000000) 76 77 /* 8237 DMA controllers */ 78 #define IO_DMA1_BASE 0x00 /* 8 bit slave DMA, channels 0..3 */ 79 #define IO_DMA2_BASE 0xC0 /* 16 bit master DMA, ch 4(=slave input)..7 */ 80 81 /* DMA controller registers */ 82 #define DMA1_CMD_REG 0x08 /* command register (w) */ 83 #define DMA1_STAT_REG 0x08 /* status register (r) */ 84 #define DMA1_REQ_REG 0x09 /* request register (w) */ 85 #define DMA1_MASK_REG 0x0A /* single-channel mask (w) */ 86 #define DMA1_MODE_REG 0x0B /* mode register (w) */ 87 #define DMA1_CLEAR_FF_REG 0x0C /* clear pointer flip-flop (w) */ 88 #define DMA1_TEMP_REG 0x0D /* Temporary Register (r) */ 89 #define DMA1_RESET_REG 0x0D /* Master Clear (w) */ 90 #define DMA1_CLR_MASK_REG 0x0E /* Clear Mask */ 91 #define DMA1_MASK_ALL_REG 0x0F /* all-channels mask (w) */ 92 93 #define DMA2_CMD_REG 0xD0 /* command register (w) */ 94 #define DMA2_STAT_REG 0xD0 /* status register (r) */ 95 #define DMA2_REQ_REG 0xD2 /* request register (w) */ 96 #define DMA2_MASK_REG 0xD4 /* single-channel mask (w) */ 97 #define DMA2_MODE_REG 0xD6 /* mode register (w) */ 98 #define DMA2_CLEAR_FF_REG 0xD8 /* clear pointer flip-flop (w) */ 99 #define DMA2_TEMP_REG 0xDA /* Temporary Register (r) */ 100 #define DMA2_RESET_REG 0xDA /* Master Clear (w) */ 101 #define DMA2_CLR_MASK_REG 0xDC /* Clear Mask */ 102 #define DMA2_MASK_ALL_REG 0xDE /* all-channels mask (w) */ 103 104 #define DMA_ADDR_0 0x00 /* DMA address registers */ 105 #define DMA_ADDR_1 0x02 106 #define DMA_ADDR_2 0x04 107 #define DMA_ADDR_3 0x06 108 #define DMA_ADDR_4 0xC0 109 #define DMA_ADDR_5 0xC4 110 #define DMA_ADDR_6 0xC8 111 #define DMA_ADDR_7 0xCC 112 113 #define DMA_CNT_0 0x01 /* DMA count registers */ 114 #define DMA_CNT_1 0x03 115 #define DMA_CNT_2 0x05 116 #define DMA_CNT_3 0x07 117 #define DMA_CNT_4 0xC2 118 #define DMA_CNT_5 0xC6 119 #define DMA_CNT_6 0xCA 120 #define DMA_CNT_7 0xCE 121 122 #define DMA_PAGE_0 0x87 /* DMA page registers */ 123 #define DMA_PAGE_1 0x83 124 #define DMA_PAGE_2 0x81 125 #define DMA_PAGE_3 0x82 126 #define DMA_PAGE_5 0x8B 127 #define DMA_PAGE_6 0x89 128 #define DMA_PAGE_7 0x8A 129 130 #define DMA_MODE_READ 0x44 /* I/O to memory, no autoinit, increment, single mode */ 131 #define DMA_MODE_WRITE 0x48 /* memory to I/O, no autoinit, increment, single mode */ 132 #define DMA_MODE_CASCADE 0xC0 /* pass thru DREQ->HRQ, DACK<-HLDA only */ 133 134 #define DMA_AUTOINIT 0x10 135 136 137 extern spinlock_t dma_spin_lock; 138 139 static __inline__ unsigned long claim_dma_lock(void) 140 { 141 unsigned long flags; 142 spin_lock_irqsave(&dma_spin_lock, flags); 143 return flags; 144 } 145 146 static __inline__ void release_dma_lock(unsigned long flags) 147 { 148 spin_unlock_irqrestore(&dma_spin_lock, flags); 149 } 150 151 /* enable/disable a specific DMA channel */ 152 static __inline__ void enable_dma(unsigned int dmanr) 153 { 154 if (dmanr<=3) 155 dma_outb(dmanr, DMA1_MASK_REG); 156 else 157 dma_outb(dmanr & 3, DMA2_MASK_REG); 158 } 159 160 static __inline__ void disable_dma(unsigned int dmanr) 161 { 162 if (dmanr<=3) 163 dma_outb(dmanr | 4, DMA1_MASK_REG); 164 else 165 dma_outb((dmanr & 3) | 4, DMA2_MASK_REG); 166 } 167 168 /* Clear the 'DMA Pointer Flip Flop'. 169 * Write 0 for LSB/MSB, 1 for MSB/LSB access. 170 * Use this once to initialize the FF to a known state. 171 * After that, keep track of it. :-) 172 * --- In order to do that, the DMA routines below should --- 173 * --- only be used while holding the DMA lock ! --- 174 */ 175 static __inline__ void clear_dma_ff(unsigned int dmanr) 176 { 177 if (dmanr<=3) 178 dma_outb(0, DMA1_CLEAR_FF_REG); 179 else 180 dma_outb(0, DMA2_CLEAR_FF_REG); 181 } 182 183 /* set mode (above) for a specific DMA channel */ 184 static __inline__ void set_dma_mode(unsigned int dmanr, char mode) 185 { 186 if (dmanr<=3) 187 dma_outb(mode | dmanr, DMA1_MODE_REG); 188 else 189 dma_outb(mode | (dmanr&3), DMA2_MODE_REG); 190 } 191 192 /* Set only the page register bits of the transfer address. 193 * This is used for successive transfers when we know the contents of 194 * the lower 16 bits of the DMA current address register, but a 64k boundary 195 * may have been crossed. 196 */ 197 static __inline__ void set_dma_page(unsigned int dmanr, char pagenr) 198 { 199 switch(dmanr) { 200 case 0: 201 dma_outb(pagenr, DMA_PAGE_0); 202 break; 203 case 1: 204 dma_outb(pagenr, DMA_PAGE_1); 205 break; 206 case 2: 207 dma_outb(pagenr, DMA_PAGE_2); 208 break; 209 case 3: 210 dma_outb(pagenr, DMA_PAGE_3); 211 break; 212 case 5: 213 dma_outb(pagenr & 0xfe, DMA_PAGE_5); 214 break; 215 case 6: 216 dma_outb(pagenr & 0xfe, DMA_PAGE_6); 217 break; 218 case 7: 219 dma_outb(pagenr & 0xfe, DMA_PAGE_7); 220 break; 221 } 222 } 223 224 225 /* Set transfer address & page bits for specific DMA channel. 226 * Assumes dma flipflop is clear. 227 */ 228 static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int a) 229 { 230 set_dma_page(dmanr, a>>16); 231 if (dmanr <= 3) { 232 dma_outb( a & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE ); 233 dma_outb( (a>>8) & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE ); 234 } else { 235 dma_outb( (a>>1) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE ); 236 dma_outb( (a>>9) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE ); 237 } 238 } 239 240 241 /* Set transfer size (max 64k for DMA0..3, 128k for DMA5..7) for 242 * a specific DMA channel. 243 * You must ensure the parameters are valid. 244 * NOTE: from a manual: "the number of transfers is one more 245 * than the initial word count"! This is taken into account. 246 * Assumes dma flip-flop is clear. 247 * NOTE 2: "count" represents _bytes_ and must be even for channels 5-7. 248 */ 249 static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count) 250 { 251 count--; 252 if (dmanr <= 3) { 253 dma_outb( count & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE ); 254 dma_outb( (count>>8) & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE ); 255 } else { 256 dma_outb( (count>>1) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE ); 257 dma_outb( (count>>9) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE ); 258 } 259 } 260 261 262 /* Get DMA residue count. After a DMA transfer, this 263 * should return zero. Reading this while a DMA transfer is 264 * still in progress will return unpredictable results. 265 * If called before the channel has been used, it may return 1. 266 * Otherwise, it returns the number of _bytes_ left to transfer. 267 * 268 * Assumes DMA flip-flop is clear. 269 */ 270 static __inline__ int get_dma_residue(unsigned int dmanr) 271 { 272 unsigned int io_port = (dmanr<=3)? ((dmanr&3)<<1) + 1 + IO_DMA1_BASE 273 : ((dmanr&3)<<2) + 2 + IO_DMA2_BASE; 274 275 /* using short to get 16-bit wrap around */ 276 unsigned short count; 277 278 count = 1 + dma_inb(io_port); 279 count += dma_inb(io_port) << 8; 280 281 return (dmanr<=3)? count : (count<<1); 282 } 283 284 285 /* These are in kernel/dma.c: */ 286 extern int request_dma(unsigned int dmanr, const char * device_id); /* reserve a DMA channel */ 287 extern void free_dma(unsigned int dmanr); /* release it again */ 288 289 /* From PCI */ 290 291 #ifdef CONFIG_PCI 292 extern int isa_dma_bridge_buggy; 293 #else 294 #define isa_dma_bridge_buggy (0) 295 #endif 296 297 #endif /* _ASM_DMA_H */ 298
