1 //===- PPCInstrAltivec.td - The PowerPC Altivec Extension --*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file describes the Altivec extension to the PowerPC instruction set. 11 // 12 //===----------------------------------------------------------------------===// 13 14 //===----------------------------------------------------------------------===// 15 // Altivec transformation functions and pattern fragments. 16 // 17 18 // Since we canonicalize buildvectors to v16i8, all vnots "-1" operands will be 19 // of that type. 20 def vnot_ppc : PatFrag<(ops node:$in), 21 (xor node:$in, (bitconvert (v16i8 immAllOnesV)))>; 22 23 def vpkuhum_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 24 (vector_shuffle node:$lhs, node:$rhs), [{ 25 return PPC::isVPKUHUMShuffleMask(cast<ShuffleVectorSDNode>(N), false); 26 }]>; 27 def vpkuwum_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 28 (vector_shuffle node:$lhs, node:$rhs), [{ 29 return PPC::isVPKUWUMShuffleMask(cast<ShuffleVectorSDNode>(N), false); 30 }]>; 31 def vpkuhum_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 32 (vector_shuffle node:$lhs, node:$rhs), [{ 33 return PPC::isVPKUHUMShuffleMask(cast<ShuffleVectorSDNode>(N), true); 34 }]>; 35 def vpkuwum_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 36 (vector_shuffle node:$lhs, node:$rhs), [{ 37 return PPC::isVPKUWUMShuffleMask(cast<ShuffleVectorSDNode>(N), true); 38 }]>; 39 40 41 def vmrglb_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 42 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 43 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 1, false); 44 }]>; 45 def vmrglh_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 46 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 47 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 2, false); 48 }]>; 49 def vmrglw_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 50 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 51 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 4, false); 52 }]>; 53 def vmrghb_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 54 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 55 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 1, false); 56 }]>; 57 def vmrghh_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 58 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 59 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 2, false); 60 }]>; 61 def vmrghw_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 62 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 63 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 4, false); 64 }]>; 65 66 67 def vmrglb_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 68 (vector_shuffle (v16i8 node:$lhs), node:$rhs), [{ 69 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 1, true); 70 }]>; 71 def vmrglh_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 72 (vector_shuffle node:$lhs, node:$rhs), [{ 73 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 2, true); 74 }]>; 75 def vmrglw_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 76 (vector_shuffle node:$lhs, node:$rhs), [{ 77 return PPC::isVMRGLShuffleMask(cast<ShuffleVectorSDNode>(N), 4, true); 78 }]>; 79 def vmrghb_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 80 (vector_shuffle node:$lhs, node:$rhs), [{ 81 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 1, true); 82 }]>; 83 def vmrghh_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 84 (vector_shuffle node:$lhs, node:$rhs), [{ 85 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 2, true); 86 }]>; 87 def vmrghw_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 88 (vector_shuffle node:$lhs, node:$rhs), [{ 89 return PPC::isVMRGHShuffleMask(cast<ShuffleVectorSDNode>(N), 4, true); 90 }]>; 91 92 93 def VSLDOI_get_imm : SDNodeXForm<vector_shuffle, [{ 94 return getI32Imm(PPC::isVSLDOIShuffleMask(N, false)); 95 }]>; 96 def vsldoi_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 97 (vector_shuffle node:$lhs, node:$rhs), [{ 98 return PPC::isVSLDOIShuffleMask(N, false) != -1; 99 }], VSLDOI_get_imm>; 100 101 102 /// VSLDOI_unary* - These are used to match vsldoi(X,X), which is turned into 103 /// vector_shuffle(X,undef,mask) by the dag combiner. 104 def VSLDOI_unary_get_imm : SDNodeXForm<vector_shuffle, [{ 105 return getI32Imm(PPC::isVSLDOIShuffleMask(N, true)); 106 }]>; 107 def vsldoi_unary_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 108 (vector_shuffle node:$lhs, node:$rhs), [{ 109 return PPC::isVSLDOIShuffleMask(N, true) != -1; 110 }], VSLDOI_unary_get_imm>; 111 112 113 // VSPLT*_get_imm xform function: convert vector_shuffle mask to VSPLT* imm. 114 def VSPLTB_get_imm : SDNodeXForm<vector_shuffle, [{ 115 return getI32Imm(PPC::getVSPLTImmediate(N, 1)); 116 }]>; 117 def vspltb_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 118 (vector_shuffle node:$lhs, node:$rhs), [{ 119 return PPC::isSplatShuffleMask(cast<ShuffleVectorSDNode>(N), 1); 120 }], VSPLTB_get_imm>; 121 def VSPLTH_get_imm : SDNodeXForm<vector_shuffle, [{ 122 return getI32Imm(PPC::getVSPLTImmediate(N, 2)); 123 }]>; 124 def vsplth_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 125 (vector_shuffle node:$lhs, node:$rhs), [{ 126 return PPC::isSplatShuffleMask(cast<ShuffleVectorSDNode>(N), 2); 127 }], VSPLTH_get_imm>; 128 def VSPLTW_get_imm : SDNodeXForm<vector_shuffle, [{ 129 return getI32Imm(PPC::getVSPLTImmediate(N, 4)); 130 }]>; 131 def vspltw_shuffle : PatFrag<(ops node:$lhs, node:$rhs), 132 (vector_shuffle node:$lhs, node:$rhs), [{ 133 return PPC::isSplatShuffleMask(cast<ShuffleVectorSDNode>(N), 4); 134 }], VSPLTW_get_imm>; 135 136 137 // VSPLTISB_get_imm xform function: convert build_vector to VSPLTISB imm. 138 def VSPLTISB_get_imm : SDNodeXForm<build_vector, [{ 139 return PPC::get_VSPLTI_elt(N, 1, *CurDAG); 140 }]>; 141 def vecspltisb : PatLeaf<(build_vector), [{ 142 return PPC::get_VSPLTI_elt(N, 1, *CurDAG).getNode() != 0; 143 }], VSPLTISB_get_imm>; 144 145 // VSPLTISH_get_imm xform function: convert build_vector to VSPLTISH imm. 146 def VSPLTISH_get_imm : SDNodeXForm<build_vector, [{ 147 return PPC::get_VSPLTI_elt(N, 2, *CurDAG); 148 }]>; 149 def vecspltish : PatLeaf<(build_vector), [{ 150 return PPC::get_VSPLTI_elt(N, 2, *CurDAG).getNode() != 0; 151 }], VSPLTISH_get_imm>; 152 153 // VSPLTISW_get_imm xform function: convert build_vector to VSPLTISW imm. 154 def VSPLTISW_get_imm : SDNodeXForm<build_vector, [{ 155 return PPC::get_VSPLTI_elt(N, 4, *CurDAG); 156 }]>; 157 def vecspltisw : PatLeaf<(build_vector), [{ 158 return PPC::get_VSPLTI_elt(N, 4, *CurDAG).getNode() != 0; 159 }], VSPLTISW_get_imm>; 160 161 def V_immneg0 : PatLeaf<(build_vector), [{ 162 return PPC::isAllNegativeZeroVector(N); 163 }]>; 164 165 //===----------------------------------------------------------------------===// 166 // Helpers for defining instructions that directly correspond to intrinsics. 167 168 // VA1a_Int - A VAForm_1a intrinsic definition. 169 class VA1a_Int<bits<6> xo, string opc, Intrinsic IntID> 170 : VAForm_1a<xo, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB, VRRC:$vC), 171 !strconcat(opc, " $vD, $vA, $vB, $vC"), VecFP, 172 [(set VRRC:$vD, (IntID VRRC:$vA, VRRC:$vB, VRRC:$vC))]>; 173 174 // VX1_Int - A VXForm_1 intrinsic definition. 175 class VX1_Int<bits<11> xo, string opc, Intrinsic IntID> 176 : VXForm_1<xo, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 177 !strconcat(opc, " $vD, $vA, $vB"), VecFP, 178 [(set VRRC:$vD, (IntID VRRC:$vA, VRRC:$vB))]>; 179 180 // VX2_Int - A VXForm_2 intrinsic definition. 181 class VX2_Int<bits<11> xo, string opc, Intrinsic IntID> 182 : VXForm_2<xo, (outs VRRC:$vD), (ins VRRC:$vB), 183 !strconcat(opc, " $vD, $vB"), VecFP, 184 [(set VRRC:$vD, (IntID VRRC:$vB))]>; 185 186 //===----------------------------------------------------------------------===// 187 // Instruction Definitions. 188 189 def DSS : DSS_Form<822, (outs), 190 (ins u5imm:$ZERO0, u5imm:$STRM,u5imm:$ZERO1,u5imm:$ZERO2), 191 "dss $STRM", LdStGeneral /*FIXME*/, []>; 192 def DSSALL : DSS_Form<822, (outs), 193 (ins u5imm:$ONE, u5imm:$ZERO0,u5imm:$ZERO1,u5imm:$ZERO2), 194 "dssall", LdStGeneral /*FIXME*/, []>; 195 def DST : DSS_Form<342, (outs), 196 (ins u5imm:$ZERO, u5imm:$STRM, GPRC:$rA, GPRC:$rB), 197 "dst $rA, $rB, $STRM", LdStGeneral /*FIXME*/, []>; 198 def DSTT : DSS_Form<342, (outs), 199 (ins u5imm:$ONE, u5imm:$STRM, GPRC:$rA, GPRC:$rB), 200 "dstt $rA, $rB, $STRM", LdStGeneral /*FIXME*/, []>; 201 def DSTST : DSS_Form<374, (outs), 202 (ins u5imm:$ZERO, u5imm:$STRM, GPRC:$rA, GPRC:$rB), 203 "dstst $rA, $rB, $STRM", LdStGeneral /*FIXME*/, []>; 204 def DSTSTT : DSS_Form<374, (outs), 205 (ins u5imm:$ONE, u5imm:$STRM, GPRC:$rA, GPRC:$rB), 206 "dststt $rA, $rB, $STRM", LdStGeneral /*FIXME*/, []>; 207 208 def DST64 : DSS_Form<342, (outs), 209 (ins u5imm:$ZERO, u5imm:$STRM, G8RC:$rA, GPRC:$rB), 210 "dst $rA, $rB, $STRM", LdStGeneral /*FIXME*/, []>; 211 def DSTT64 : DSS_Form<342, (outs), 212 (ins u5imm:$ONE, u5imm:$STRM, G8RC:$rA, GPRC:$rB), 213 "dstt $rA, $rB, $STRM", LdStGeneral /*FIXME*/, []>; 214 def DSTST64 : DSS_Form<374, (outs), 215 (ins u5imm:$ZERO, u5imm:$STRM, G8RC:$rA, GPRC:$rB), 216 "dstst $rA, $rB, $STRM", LdStGeneral /*FIXME*/, []>; 217 def DSTSTT64 : DSS_Form<374, (outs), 218 (ins u5imm:$ONE, u5imm:$STRM, G8RC:$rA, GPRC:$rB), 219 "dststt $rA, $rB, $STRM", LdStGeneral /*FIXME*/, []>; 220 221 def MFVSCR : VXForm_4<1540, (outs VRRC:$vD), (ins), 222 "mfvscr $vD", LdStGeneral, 223 [(set VRRC:$vD, (int_ppc_altivec_mfvscr))]>; 224 def MTVSCR : VXForm_5<1604, (outs), (ins VRRC:$vB), 225 "mtvscr $vB", LdStGeneral, 226 [(int_ppc_altivec_mtvscr VRRC:$vB)]>; 227 228 let canFoldAsLoad = 1, PPC970_Unit = 2 in { // Loads. 229 def LVEBX: XForm_1<31, 7, (outs VRRC:$vD), (ins memrr:$src), 230 "lvebx $vD, $src", LdStGeneral, 231 [(set VRRC:$vD, (int_ppc_altivec_lvebx xoaddr:$src))]>; 232 def LVEHX: XForm_1<31, 39, (outs VRRC:$vD), (ins memrr:$src), 233 "lvehx $vD, $src", LdStGeneral, 234 [(set VRRC:$vD, (int_ppc_altivec_lvehx xoaddr:$src))]>; 235 def LVEWX: XForm_1<31, 71, (outs VRRC:$vD), (ins memrr:$src), 236 "lvewx $vD, $src", LdStGeneral, 237 [(set VRRC:$vD, (int_ppc_altivec_lvewx xoaddr:$src))]>; 238 def LVX : XForm_1<31, 103, (outs VRRC:$vD), (ins memrr:$src), 239 "lvx $vD, $src", LdStGeneral, 240 [(set VRRC:$vD, (int_ppc_altivec_lvx xoaddr:$src))]>; 241 def LVXL : XForm_1<31, 359, (outs VRRC:$vD), (ins memrr:$src), 242 "lvxl $vD, $src", LdStGeneral, 243 [(set VRRC:$vD, (int_ppc_altivec_lvxl xoaddr:$src))]>; 244 } 245 246 def LVSL : XForm_1<31, 6, (outs VRRC:$vD), (ins memrr:$src), 247 "lvsl $vD, $src", LdStGeneral, 248 [(set VRRC:$vD, (int_ppc_altivec_lvsl xoaddr:$src))]>, 249 PPC970_Unit_LSU; 250 def LVSR : XForm_1<31, 38, (outs VRRC:$vD), (ins memrr:$src), 251 "lvsr $vD, $src", LdStGeneral, 252 [(set VRRC:$vD, (int_ppc_altivec_lvsr xoaddr:$src))]>, 253 PPC970_Unit_LSU; 254 255 let PPC970_Unit = 2 in { // Stores. 256 def STVEBX: XForm_8<31, 135, (outs), (ins VRRC:$rS, memrr:$dst), 257 "stvebx $rS, $dst", LdStGeneral, 258 [(int_ppc_altivec_stvebx VRRC:$rS, xoaddr:$dst)]>; 259 def STVEHX: XForm_8<31, 167, (outs), (ins VRRC:$rS, memrr:$dst), 260 "stvehx $rS, $dst", LdStGeneral, 261 [(int_ppc_altivec_stvehx VRRC:$rS, xoaddr:$dst)]>; 262 def STVEWX: XForm_8<31, 199, (outs), (ins VRRC:$rS, memrr:$dst), 263 "stvewx $rS, $dst", LdStGeneral, 264 [(int_ppc_altivec_stvewx VRRC:$rS, xoaddr:$dst)]>; 265 def STVX : XForm_8<31, 231, (outs), (ins VRRC:$rS, memrr:$dst), 266 "stvx $rS, $dst", LdStGeneral, 267 [(int_ppc_altivec_stvx VRRC:$rS, xoaddr:$dst)]>; 268 def STVXL : XForm_8<31, 487, (outs), (ins VRRC:$rS, memrr:$dst), 269 "stvxl $rS, $dst", LdStGeneral, 270 [(int_ppc_altivec_stvxl VRRC:$rS, xoaddr:$dst)]>; 271 } 272 273 let PPC970_Unit = 5 in { // VALU Operations. 274 // VA-Form instructions. 3-input AltiVec ops. 275 def VMADDFP : VAForm_1<46, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vC, VRRC:$vB), 276 "vmaddfp $vD, $vA, $vC, $vB", VecFP, 277 [(set VRRC:$vD, (fadd (fmul VRRC:$vA, VRRC:$vC), 278 VRRC:$vB))]>, 279 Requires<[FPContractions]>; 280 def VNMSUBFP: VAForm_1<47, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vC, VRRC:$vB), 281 "vnmsubfp $vD, $vA, $vC, $vB", VecFP, 282 [(set VRRC:$vD, (fsub V_immneg0, 283 (fsub (fmul VRRC:$vA, VRRC:$vC), 284 VRRC:$vB)))]>, 285 Requires<[FPContractions]>; 286 287 def VMHADDSHS : VA1a_Int<32, "vmhaddshs", int_ppc_altivec_vmhaddshs>; 288 def VMHRADDSHS : VA1a_Int<33, "vmhraddshs", int_ppc_altivec_vmhraddshs>; 289 def VMLADDUHM : VA1a_Int<34, "vmladduhm", int_ppc_altivec_vmladduhm>; 290 def VPERM : VA1a_Int<43, "vperm", int_ppc_altivec_vperm>; 291 def VSEL : VA1a_Int<42, "vsel", int_ppc_altivec_vsel>; 292 293 // Shuffles. 294 def VSLDOI : VAForm_2<44, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB, u5imm:$SH), 295 "vsldoi $vD, $vA, $vB, $SH", VecFP, 296 [(set VRRC:$vD, 297 (vsldoi_shuffle:$SH (v16i8 VRRC:$vA), VRRC:$vB))]>; 298 299 // VX-Form instructions. AltiVec arithmetic ops. 300 def VADDFP : VXForm_1<10, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 301 "vaddfp $vD, $vA, $vB", VecFP, 302 [(set VRRC:$vD, (fadd VRRC:$vA, VRRC:$vB))]>; 303 304 def VADDUBM : VXForm_1<0, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 305 "vaddubm $vD, $vA, $vB", VecGeneral, 306 [(set VRRC:$vD, (add (v16i8 VRRC:$vA), VRRC:$vB))]>; 307 def VADDUHM : VXForm_1<64, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 308 "vadduhm $vD, $vA, $vB", VecGeneral, 309 [(set VRRC:$vD, (add (v8i16 VRRC:$vA), VRRC:$vB))]>; 310 def VADDUWM : VXForm_1<128, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 311 "vadduwm $vD, $vA, $vB", VecGeneral, 312 [(set VRRC:$vD, (add (v4i32 VRRC:$vA), VRRC:$vB))]>; 313 314 def VADDCUW : VX1_Int<384, "vaddcuw", int_ppc_altivec_vaddcuw>; 315 def VADDSBS : VX1_Int<768, "vaddsbs", int_ppc_altivec_vaddsbs>; 316 def VADDSHS : VX1_Int<832, "vaddshs", int_ppc_altivec_vaddshs>; 317 def VADDSWS : VX1_Int<896, "vaddsws", int_ppc_altivec_vaddsws>; 318 def VADDUBS : VX1_Int<512, "vaddubs", int_ppc_altivec_vaddubs>; 319 def VADDUHS : VX1_Int<576, "vadduhs", int_ppc_altivec_vadduhs>; 320 def VADDUWS : VX1_Int<640, "vadduws", int_ppc_altivec_vadduws>; 321 322 323 def VAND : VXForm_1<1028, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 324 "vand $vD, $vA, $vB", VecFP, 325 [(set VRRC:$vD, (and (v4i32 VRRC:$vA), VRRC:$vB))]>; 326 def VANDC : VXForm_1<1092, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 327 "vandc $vD, $vA, $vB", VecFP, 328 [(set VRRC:$vD, (and (v4i32 VRRC:$vA), 329 (vnot_ppc VRRC:$vB)))]>; 330 331 def VCFSX : VXForm_1<842, (outs VRRC:$vD), (ins u5imm:$UIMM, VRRC:$vB), 332 "vcfsx $vD, $vB, $UIMM", VecFP, 333 [(set VRRC:$vD, 334 (int_ppc_altivec_vcfsx VRRC:$vB, imm:$UIMM))]>; 335 def VCFUX : VXForm_1<778, (outs VRRC:$vD), (ins u5imm:$UIMM, VRRC:$vB), 336 "vcfux $vD, $vB, $UIMM", VecFP, 337 [(set VRRC:$vD, 338 (int_ppc_altivec_vcfux VRRC:$vB, imm:$UIMM))]>; 339 def VCTSXS : VXForm_1<970, (outs VRRC:$vD), (ins u5imm:$UIMM, VRRC:$vB), 340 "vctsxs $vD, $vB, $UIMM", VecFP, 341 [(set VRRC:$vD, 342 (int_ppc_altivec_vctsxs VRRC:$vB, imm:$UIMM))]>; 343 def VCTUXS : VXForm_1<906, (outs VRRC:$vD), (ins u5imm:$UIMM, VRRC:$vB), 344 "vctuxs $vD, $vB, $UIMM", VecFP, 345 [(set VRRC:$vD, 346 (int_ppc_altivec_vctuxs VRRC:$vB, imm:$UIMM))]>; 347 def VEXPTEFP : VX2_Int<394, "vexptefp", int_ppc_altivec_vexptefp>; 348 def VLOGEFP : VX2_Int<458, "vlogefp", int_ppc_altivec_vlogefp>; 349 350 def VAVGSB : VX1_Int<1282, "vavgsb", int_ppc_altivec_vavgsb>; 351 def VAVGSH : VX1_Int<1346, "vavgsh", int_ppc_altivec_vavgsh>; 352 def VAVGSW : VX1_Int<1410, "vavgsw", int_ppc_altivec_vavgsw>; 353 def VAVGUB : VX1_Int<1026, "vavgub", int_ppc_altivec_vavgub>; 354 def VAVGUH : VX1_Int<1090, "vavguh", int_ppc_altivec_vavguh>; 355 def VAVGUW : VX1_Int<1154, "vavguw", int_ppc_altivec_vavguw>; 356 357 def VMAXFP : VX1_Int<1034, "vmaxfp", int_ppc_altivec_vmaxfp>; 358 def VMAXSB : VX1_Int< 258, "vmaxsb", int_ppc_altivec_vmaxsb>; 359 def VMAXSH : VX1_Int< 322, "vmaxsh", int_ppc_altivec_vmaxsh>; 360 def VMAXSW : VX1_Int< 386, "vmaxsw", int_ppc_altivec_vmaxsw>; 361 def VMAXUB : VX1_Int< 2, "vmaxub", int_ppc_altivec_vmaxub>; 362 def VMAXUH : VX1_Int< 66, "vmaxuh", int_ppc_altivec_vmaxuh>; 363 def VMAXUW : VX1_Int< 130, "vmaxuw", int_ppc_altivec_vmaxuw>; 364 def VMINFP : VX1_Int<1098, "vminfp", int_ppc_altivec_vminfp>; 365 def VMINSB : VX1_Int< 770, "vminsb", int_ppc_altivec_vminsb>; 366 def VMINSH : VX1_Int< 834, "vminsh", int_ppc_altivec_vminsh>; 367 def VMINSW : VX1_Int< 898, "vminsw", int_ppc_altivec_vminsw>; 368 def VMINUB : VX1_Int< 514, "vminub", int_ppc_altivec_vminub>; 369 def VMINUH : VX1_Int< 578, "vminuh", int_ppc_altivec_vminuh>; 370 def VMINUW : VX1_Int< 642, "vminuw", int_ppc_altivec_vminuw>; 371 372 def VMRGHB : VXForm_1< 12, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 373 "vmrghb $vD, $vA, $vB", VecFP, 374 [(set VRRC:$vD, (vmrghb_shuffle VRRC:$vA, VRRC:$vB))]>; 375 def VMRGHH : VXForm_1< 76, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 376 "vmrghh $vD, $vA, $vB", VecFP, 377 [(set VRRC:$vD, (vmrghh_shuffle VRRC:$vA, VRRC:$vB))]>; 378 def VMRGHW : VXForm_1<140, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 379 "vmrghw $vD, $vA, $vB", VecFP, 380 [(set VRRC:$vD, (vmrghw_shuffle VRRC:$vA, VRRC:$vB))]>; 381 def VMRGLB : VXForm_1<268, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 382 "vmrglb $vD, $vA, $vB", VecFP, 383 [(set VRRC:$vD, (vmrglb_shuffle VRRC:$vA, VRRC:$vB))]>; 384 def VMRGLH : VXForm_1<332, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 385 "vmrglh $vD, $vA, $vB", VecFP, 386 [(set VRRC:$vD, (vmrglh_shuffle VRRC:$vA, VRRC:$vB))]>; 387 def VMRGLW : VXForm_1<396, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 388 "vmrglw $vD, $vA, $vB", VecFP, 389 [(set VRRC:$vD, (vmrglw_shuffle VRRC:$vA, VRRC:$vB))]>; 390 391 def VMSUMMBM : VA1a_Int<37, "vmsummbm", int_ppc_altivec_vmsummbm>; 392 def VMSUMSHM : VA1a_Int<40, "vmsumshm", int_ppc_altivec_vmsumshm>; 393 def VMSUMSHS : VA1a_Int<41, "vmsumshs", int_ppc_altivec_vmsumshs>; 394 def VMSUMUBM : VA1a_Int<36, "vmsumubm", int_ppc_altivec_vmsumubm>; 395 def VMSUMUHM : VA1a_Int<38, "vmsumuhm", int_ppc_altivec_vmsumuhm>; 396 def VMSUMUHS : VA1a_Int<39, "vmsumuhs", int_ppc_altivec_vmsumuhs>; 397 398 def VMULESB : VX1_Int<776, "vmulesb", int_ppc_altivec_vmulesb>; 399 def VMULESH : VX1_Int<840, "vmulesh", int_ppc_altivec_vmulesh>; 400 def VMULEUB : VX1_Int<520, "vmuleub", int_ppc_altivec_vmuleub>; 401 def VMULEUH : VX1_Int<584, "vmuleuh", int_ppc_altivec_vmuleuh>; 402 def VMULOSB : VX1_Int<264, "vmulosb", int_ppc_altivec_vmulosb>; 403 def VMULOSH : VX1_Int<328, "vmulosh", int_ppc_altivec_vmulosh>; 404 def VMULOUB : VX1_Int< 8, "vmuloub", int_ppc_altivec_vmuloub>; 405 def VMULOUH : VX1_Int< 72, "vmulouh", int_ppc_altivec_vmulouh>; 406 407 def VREFP : VX2_Int<266, "vrefp", int_ppc_altivec_vrefp>; 408 def VRFIM : VX2_Int<714, "vrfim", int_ppc_altivec_vrfim>; 409 def VRFIN : VX2_Int<522, "vrfin", int_ppc_altivec_vrfin>; 410 def VRFIP : VX2_Int<650, "vrfip", int_ppc_altivec_vrfip>; 411 def VRFIZ : VX2_Int<586, "vrfiz", int_ppc_altivec_vrfiz>; 412 def VRSQRTEFP : VX2_Int<330, "vrsqrtefp", int_ppc_altivec_vrsqrtefp>; 413 414 def VSUBCUW : VX1_Int<74, "vsubcuw", int_ppc_altivec_vsubcuw>; 415 416 def VSUBFP : VXForm_1<74, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 417 "vsubfp $vD, $vA, $vB", VecGeneral, 418 [(set VRRC:$vD, (fsub VRRC:$vA, VRRC:$vB))]>; 419 def VSUBUBM : VXForm_1<1024, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 420 "vsububm $vD, $vA, $vB", VecGeneral, 421 [(set VRRC:$vD, (sub (v16i8 VRRC:$vA), VRRC:$vB))]>; 422 def VSUBUHM : VXForm_1<1088, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 423 "vsubuhm $vD, $vA, $vB", VecGeneral, 424 [(set VRRC:$vD, (sub (v8i16 VRRC:$vA), VRRC:$vB))]>; 425 def VSUBUWM : VXForm_1<1152, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 426 "vsubuwm $vD, $vA, $vB", VecGeneral, 427 [(set VRRC:$vD, (sub (v4i32 VRRC:$vA), VRRC:$vB))]>; 428 429 def VSUBSBS : VX1_Int<1792, "vsubsbs" , int_ppc_altivec_vsubsbs>; 430 def VSUBSHS : VX1_Int<1856, "vsubshs" , int_ppc_altivec_vsubshs>; 431 def VSUBSWS : VX1_Int<1920, "vsubsws" , int_ppc_altivec_vsubsws>; 432 def VSUBUBS : VX1_Int<1536, "vsububs" , int_ppc_altivec_vsububs>; 433 def VSUBUHS : VX1_Int<1600, "vsubuhs" , int_ppc_altivec_vsubuhs>; 434 def VSUBUWS : VX1_Int<1664, "vsubuws" , int_ppc_altivec_vsubuws>; 435 def VSUMSWS : VX1_Int<1928, "vsumsws" , int_ppc_altivec_vsumsws>; 436 def VSUM2SWS: VX1_Int<1672, "vsum2sws", int_ppc_altivec_vsum2sws>; 437 def VSUM4SBS: VX1_Int<1672, "vsum4sbs", int_ppc_altivec_vsum4sbs>; 438 def VSUM4SHS: VX1_Int<1608, "vsum4shs", int_ppc_altivec_vsum4shs>; 439 def VSUM4UBS: VX1_Int<1544, "vsum4ubs", int_ppc_altivec_vsum4ubs>; 440 441 def VNOR : VXForm_1<1284, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 442 "vnor $vD, $vA, $vB", VecFP, 443 [(set VRRC:$vD, (vnot_ppc (or (v4i32 VRRC:$vA), 444 VRRC:$vB)))]>; 445 def VOR : VXForm_1<1156, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 446 "vor $vD, $vA, $vB", VecFP, 447 [(set VRRC:$vD, (or (v4i32 VRRC:$vA), VRRC:$vB))]>; 448 def VXOR : VXForm_1<1220, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 449 "vxor $vD, $vA, $vB", VecFP, 450 [(set VRRC:$vD, (xor (v4i32 VRRC:$vA), VRRC:$vB))]>; 451 452 def VRLB : VX1_Int< 4, "vrlb", int_ppc_altivec_vrlb>; 453 def VRLH : VX1_Int< 68, "vrlh", int_ppc_altivec_vrlh>; 454 def VRLW : VX1_Int< 132, "vrlw", int_ppc_altivec_vrlw>; 455 456 def VSL : VX1_Int< 452, "vsl" , int_ppc_altivec_vsl >; 457 def VSLO : VX1_Int<1036, "vslo", int_ppc_altivec_vslo>; 458 def VSLB : VX1_Int< 260, "vslb", int_ppc_altivec_vslb>; 459 def VSLH : VX1_Int< 324, "vslh", int_ppc_altivec_vslh>; 460 def VSLW : VX1_Int< 388, "vslw", int_ppc_altivec_vslw>; 461 462 def VSPLTB : VXForm_1<524, (outs VRRC:$vD), (ins u5imm:$UIMM, VRRC:$vB), 463 "vspltb $vD, $vB, $UIMM", VecPerm, 464 [(set VRRC:$vD, 465 (vspltb_shuffle:$UIMM (v16i8 VRRC:$vB), (undef)))]>; 466 def VSPLTH : VXForm_1<588, (outs VRRC:$vD), (ins u5imm:$UIMM, VRRC:$vB), 467 "vsplth $vD, $vB, $UIMM", VecPerm, 468 [(set VRRC:$vD, 469 (vsplth_shuffle:$UIMM (v16i8 VRRC:$vB), (undef)))]>; 470 def VSPLTW : VXForm_1<652, (outs VRRC:$vD), (ins u5imm:$UIMM, VRRC:$vB), 471 "vspltw $vD, $vB, $UIMM", VecPerm, 472 [(set VRRC:$vD, 473 (vspltw_shuffle:$UIMM (v16i8 VRRC:$vB), (undef)))]>; 474 475 def VSR : VX1_Int< 708, "vsr" , int_ppc_altivec_vsr>; 476 def VSRO : VX1_Int<1100, "vsro" , int_ppc_altivec_vsro>; 477 def VSRAB : VX1_Int< 772, "vsrab", int_ppc_altivec_vsrab>; 478 def VSRAH : VX1_Int< 836, "vsrah", int_ppc_altivec_vsrah>; 479 def VSRAW : VX1_Int< 900, "vsraw", int_ppc_altivec_vsraw>; 480 def VSRB : VX1_Int< 516, "vsrb" , int_ppc_altivec_vsrb>; 481 def VSRH : VX1_Int< 580, "vsrh" , int_ppc_altivec_vsrh>; 482 def VSRW : VX1_Int< 644, "vsrw" , int_ppc_altivec_vsrw>; 483 484 485 def VSPLTISB : VXForm_3<780, (outs VRRC:$vD), (ins s5imm:$SIMM), 486 "vspltisb $vD, $SIMM", VecPerm, 487 [(set VRRC:$vD, (v16i8 vecspltisb:$SIMM))]>; 488 def VSPLTISH : VXForm_3<844, (outs VRRC:$vD), (ins s5imm:$SIMM), 489 "vspltish $vD, $SIMM", VecPerm, 490 [(set VRRC:$vD, (v8i16 vecspltish:$SIMM))]>; 491 def VSPLTISW : VXForm_3<908, (outs VRRC:$vD), (ins s5imm:$SIMM), 492 "vspltisw $vD, $SIMM", VecPerm, 493 [(set VRRC:$vD, (v4i32 vecspltisw:$SIMM))]>; 494 495 // Vector Pack. 496 def VPKPX : VX1_Int<782, "vpkpx", int_ppc_altivec_vpkpx>; 497 def VPKSHSS : VX1_Int<398, "vpkshss", int_ppc_altivec_vpkshss>; 498 def VPKSHUS : VX1_Int<270, "vpkshus", int_ppc_altivec_vpkshus>; 499 def VPKSWSS : VX1_Int<462, "vpkswss", int_ppc_altivec_vpkswss>; 500 def VPKSWUS : VX1_Int<334, "vpkswus", int_ppc_altivec_vpkswus>; 501 def VPKUHUM : VXForm_1<14, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 502 "vpkuhum $vD, $vA, $vB", VecFP, 503 [(set VRRC:$vD, 504 (vpkuhum_shuffle (v16i8 VRRC:$vA), VRRC:$vB))]>; 505 def VPKUHUS : VX1_Int<142, "vpkuhus", int_ppc_altivec_vpkuhus>; 506 def VPKUWUM : VXForm_1<78, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB), 507 "vpkuwum $vD, $vA, $vB", VecFP, 508 [(set VRRC:$vD, 509 (vpkuwum_shuffle (v16i8 VRRC:$vA), VRRC:$vB))]>; 510 def VPKUWUS : VX1_Int<206, "vpkuwus", int_ppc_altivec_vpkuwus>; 511 512 // Vector Unpack. 513 def VUPKHPX : VX2_Int<846, "vupkhpx", int_ppc_altivec_vupkhpx>; 514 def VUPKHSB : VX2_Int<526, "vupkhsb", int_ppc_altivec_vupkhsb>; 515 def VUPKHSH : VX2_Int<590, "vupkhsh", int_ppc_altivec_vupkhsh>; 516 def VUPKLPX : VX2_Int<974, "vupklpx", int_ppc_altivec_vupklpx>; 517 def VUPKLSB : VX2_Int<654, "vupklsb", int_ppc_altivec_vupklsb>; 518 def VUPKLSH : VX2_Int<718, "vupklsh", int_ppc_altivec_vupklsh>; 519 520 521 // Altivec Comparisons. 522 523 class VCMP<bits<10> xo, string asmstr, ValueType Ty> 524 : VXRForm_1<xo, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),asmstr,VecFPCompare, 525 [(set VRRC:$vD, (Ty (PPCvcmp VRRC:$vA, VRRC:$vB, xo)))]>; 526 class VCMPo<bits<10> xo, string asmstr, ValueType Ty> 527 : VXRForm_1<xo, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),asmstr,VecFPCompare, 528 [(set VRRC:$vD, (Ty (PPCvcmp_o VRRC:$vA, VRRC:$vB, xo)))]> { 529 let Defs = [CR6]; 530 let RC = 1; 531 } 532 533 // f32 element comparisons.0 534 def VCMPBFP : VCMP <966, "vcmpbfp $vD, $vA, $vB" , v4f32>; 535 def VCMPBFPo : VCMPo<966, "vcmpbfp. $vD, $vA, $vB" , v4f32>; 536 def VCMPEQFP : VCMP <198, "vcmpeqfp $vD, $vA, $vB" , v4f32>; 537 def VCMPEQFPo : VCMPo<198, "vcmpeqfp. $vD, $vA, $vB", v4f32>; 538 def VCMPGEFP : VCMP <454, "vcmpgefp $vD, $vA, $vB" , v4f32>; 539 def VCMPGEFPo : VCMPo<454, "vcmpgefp. $vD, $vA, $vB", v4f32>; 540 def VCMPGTFP : VCMP <710, "vcmpgtfp $vD, $vA, $vB" , v4f32>; 541 def VCMPGTFPo : VCMPo<710, "vcmpgtfp. $vD, $vA, $vB", v4f32>; 542 543 // i8 element comparisons. 544 def VCMPEQUB : VCMP < 6, "vcmpequb $vD, $vA, $vB" , v16i8>; 545 def VCMPEQUBo : VCMPo< 6, "vcmpequb. $vD, $vA, $vB", v16i8>; 546 def VCMPGTSB : VCMP <774, "vcmpgtsb $vD, $vA, $vB" , v16i8>; 547 def VCMPGTSBo : VCMPo<774, "vcmpgtsb. $vD, $vA, $vB", v16i8>; 548 def VCMPGTUB : VCMP <518, "vcmpgtub $vD, $vA, $vB" , v16i8>; 549 def VCMPGTUBo : VCMPo<518, "vcmpgtub. $vD, $vA, $vB", v16i8>; 550 551 // i16 element comparisons. 552 def VCMPEQUH : VCMP < 70, "vcmpequh $vD, $vA, $vB" , v8i16>; 553 def VCMPEQUHo : VCMPo< 70, "vcmpequh. $vD, $vA, $vB", v8i16>; 554 def VCMPGTSH : VCMP <838, "vcmpgtsh $vD, $vA, $vB" , v8i16>; 555 def VCMPGTSHo : VCMPo<838, "vcmpgtsh. $vD, $vA, $vB", v8i16>; 556 def VCMPGTUH : VCMP <582, "vcmpgtuh $vD, $vA, $vB" , v8i16>; 557 def VCMPGTUHo : VCMPo<582, "vcmpgtuh. $vD, $vA, $vB", v8i16>; 558 559 // i32 element comparisons. 560 def VCMPEQUW : VCMP <134, "vcmpequw $vD, $vA, $vB" , v4i32>; 561 def VCMPEQUWo : VCMPo<134, "vcmpequw. $vD, $vA, $vB", v4i32>; 562 def VCMPGTSW : VCMP <902, "vcmpgtsw $vD, $vA, $vB" , v4i32>; 563 def VCMPGTSWo : VCMPo<902, "vcmpgtsw. $vD, $vA, $vB", v4i32>; 564 def VCMPGTUW : VCMP <646, "vcmpgtuw $vD, $vA, $vB" , v4i32>; 565 def VCMPGTUWo : VCMPo<646, "vcmpgtuw. $vD, $vA, $vB", v4i32>; 566 567 def V_SET0 : VXForm_setzero<1220, (outs VRRC:$vD), (ins), 568 "vxor $vD, $vD, $vD", VecFP, 569 [(set VRRC:$vD, (v4i32 immAllZerosV))]>; 570 } 571 572 //===----------------------------------------------------------------------===// 573 // Additional Altivec Patterns 574 // 575 576 // DS* intrinsics 577 def : Pat<(int_ppc_altivec_dssall), (DSSALL 1, 0, 0, 0)>; 578 def : Pat<(int_ppc_altivec_dss imm:$STRM), (DSS 0, imm:$STRM, 0, 0)>; 579 580 // * 32-bit 581 def : Pat<(int_ppc_altivec_dst GPRC:$rA, GPRC:$rB, imm:$STRM), 582 (DST 0, imm:$STRM, GPRC:$rA, GPRC:$rB)>; 583 def : Pat<(int_ppc_altivec_dstt GPRC:$rA, GPRC:$rB, imm:$STRM), 584 (DSTT 1, imm:$STRM, GPRC:$rA, GPRC:$rB)>; 585 def : Pat<(int_ppc_altivec_dstst GPRC:$rA, GPRC:$rB, imm:$STRM), 586 (DSTST 0, imm:$STRM, GPRC:$rA, GPRC:$rB)>; 587 def : Pat<(int_ppc_altivec_dststt GPRC:$rA, GPRC:$rB, imm:$STRM), 588 (DSTSTT 1, imm:$STRM, GPRC:$rA, GPRC:$rB)>; 589 590 // * 64-bit 591 def : Pat<(int_ppc_altivec_dst G8RC:$rA, GPRC:$rB, imm:$STRM), 592 (DST64 0, imm:$STRM, (i64 G8RC:$rA), GPRC:$rB)>; 593 def : Pat<(int_ppc_altivec_dstt G8RC:$rA, GPRC:$rB, imm:$STRM), 594 (DSTT64 1, imm:$STRM, (i64 G8RC:$rA), GPRC:$rB)>; 595 def : Pat<(int_ppc_altivec_dstst G8RC:$rA, GPRC:$rB, imm:$STRM), 596 (DSTST64 0, imm:$STRM, (i64 G8RC:$rA), GPRC:$rB)>; 597 def : Pat<(int_ppc_altivec_dststt G8RC:$rA, GPRC:$rB, imm:$STRM), 598 (DSTSTT64 1, imm:$STRM, (i64 G8RC:$rA), GPRC:$rB)>; 599 600 // Loads. 601 def : Pat<(v4i32 (load xoaddr:$src)), (LVX xoaddr:$src)>; 602 603 // Stores. 604 def : Pat<(store (v4i32 VRRC:$rS), xoaddr:$dst), 605 (STVX (v4i32 VRRC:$rS), xoaddr:$dst)>; 606 607 // Bit conversions. 608 def : Pat<(v16i8 (bitconvert (v8i16 VRRC:$src))), (v16i8 VRRC:$src)>; 609 def : Pat<(v16i8 (bitconvert (v4i32 VRRC:$src))), (v16i8 VRRC:$src)>; 610 def : Pat<(v16i8 (bitconvert (v4f32 VRRC:$src))), (v16i8 VRRC:$src)>; 611 612 def : Pat<(v8i16 (bitconvert (v16i8 VRRC:$src))), (v8i16 VRRC:$src)>; 613 def : Pat<(v8i16 (bitconvert (v4i32 VRRC:$src))), (v8i16 VRRC:$src)>; 614 def : Pat<(v8i16 (bitconvert (v4f32 VRRC:$src))), (v8i16 VRRC:$src)>; 615 616 def : Pat<(v4i32 (bitconvert (v16i8 VRRC:$src))), (v4i32 VRRC:$src)>; 617 def : Pat<(v4i32 (bitconvert (v8i16 VRRC:$src))), (v4i32 VRRC:$src)>; 618 def : Pat<(v4i32 (bitconvert (v4f32 VRRC:$src))), (v4i32 VRRC:$src)>; 619 620 def : Pat<(v4f32 (bitconvert (v16i8 VRRC:$src))), (v4f32 VRRC:$src)>; 621 def : Pat<(v4f32 (bitconvert (v8i16 VRRC:$src))), (v4f32 VRRC:$src)>; 622 def : Pat<(v4f32 (bitconvert (v4i32 VRRC:$src))), (v4f32 VRRC:$src)>; 623 624 // Shuffles. 625 626 // Match vsldoi(x,x), vpkuwum(x,x), vpkuhum(x,x) 627 def:Pat<(vsldoi_unary_shuffle:$in (v16i8 VRRC:$vA), undef), 628 (VSLDOI VRRC:$vA, VRRC:$vA, (VSLDOI_unary_get_imm VRRC:$in))>; 629 def:Pat<(vpkuwum_unary_shuffle (v16i8 VRRC:$vA), undef), 630 (VPKUWUM VRRC:$vA, VRRC:$vA)>; 631 def:Pat<(vpkuhum_unary_shuffle (v16i8 VRRC:$vA), undef), 632 (VPKUHUM VRRC:$vA, VRRC:$vA)>; 633 634 // Match vmrg*(x,x) 635 def:Pat<(vmrglb_unary_shuffle (v16i8 VRRC:$vA), undef), 636 (VMRGLB VRRC:$vA, VRRC:$vA)>; 637 def:Pat<(vmrglh_unary_shuffle (v16i8 VRRC:$vA), undef), 638 (VMRGLH VRRC:$vA, VRRC:$vA)>; 639 def:Pat<(vmrglw_unary_shuffle (v16i8 VRRC:$vA), undef), 640 (VMRGLW VRRC:$vA, VRRC:$vA)>; 641 def:Pat<(vmrghb_unary_shuffle (v16i8 VRRC:$vA), undef), 642 (VMRGHB VRRC:$vA, VRRC:$vA)>; 643 def:Pat<(vmrghh_unary_shuffle (v16i8 VRRC:$vA), undef), 644 (VMRGHH VRRC:$vA, VRRC:$vA)>; 645 def:Pat<(vmrghw_unary_shuffle (v16i8 VRRC:$vA), undef), 646 (VMRGHW VRRC:$vA, VRRC:$vA)>; 647 648 // Logical Operations 649 def : Pat<(v4i32 (vnot_ppc VRRC:$vA)), (VNOR VRRC:$vA, VRRC:$vA)>; 650 651 def : Pat<(v4i32 (vnot_ppc (or VRRC:$A, VRRC:$B))), 652 (VNOR VRRC:$A, VRRC:$B)>; 653 def : Pat<(v4i32 (and VRRC:$A, (vnot_ppc VRRC:$B))), 654 (VANDC VRRC:$A, VRRC:$B)>; 655 656 def : Pat<(fmul VRRC:$vA, VRRC:$vB), 657 (VMADDFP VRRC:$vA, VRRC:$vB, (v4i32 (V_SET0)))>; 658 659 // Fused multiply add and multiply sub for packed float. These are represented 660 // separately from the real instructions above, for operations that must have 661 // the additional precision, such as Newton-Rhapson (used by divide, sqrt) 662 def : Pat<(PPCvmaddfp VRRC:$A, VRRC:$B, VRRC:$C), 663 (VMADDFP VRRC:$A, VRRC:$B, VRRC:$C)>; 664 def : Pat<(PPCvnmsubfp VRRC:$A, VRRC:$B, VRRC:$C), 665 (VNMSUBFP VRRC:$A, VRRC:$B, VRRC:$C)>; 666 667 def : Pat<(int_ppc_altivec_vmaddfp VRRC:$A, VRRC:$B, VRRC:$C), 668 (VMADDFP VRRC:$A, VRRC:$B, VRRC:$C)>; 669 def : Pat<(int_ppc_altivec_vnmsubfp VRRC:$A, VRRC:$B, VRRC:$C), 670 (VNMSUBFP VRRC:$A, VRRC:$B, VRRC:$C)>; 671 672 def : Pat<(PPCvperm (v16i8 VRRC:$vA), VRRC:$vB, VRRC:$vC), 673 (VPERM VRRC:$vA, VRRC:$vB, VRRC:$vC)>; 674 675 // Vector shifts 676 def : Pat<(v16i8 (shl (v16i8 VRRC:$vA), (v16i8 VRRC:$vB))), 677 (v16i8 (VSLB VRRC:$vA, VRRC:$vB))>; 678 def : Pat<(v8i16 (shl (v8i16 VRRC:$vA), (v8i16 VRRC:$vB))), 679 (v8i16 (VSLH VRRC:$vA, VRRC:$vB))>; 680 def : Pat<(v4i32 (shl (v4i32 VRRC:$vA), (v4i32 VRRC:$vB))), 681 (v4i32 (VSLW VRRC:$vA, VRRC:$vB))>; 682 683 def : Pat<(v16i8 (srl (v16i8 VRRC:$vA), (v16i8 VRRC:$vB))), 684 (v16i8 (VSRB VRRC:$vA, VRRC:$vB))>; 685 def : Pat<(v8i16 (srl (v8i16 VRRC:$vA), (v8i16 VRRC:$vB))), 686 (v8i16 (VSRH VRRC:$vA, VRRC:$vB))>; 687 def : Pat<(v4i32 (srl (v4i32 VRRC:$vA), (v4i32 VRRC:$vB))), 688 (v4i32 (VSRW VRRC:$vA, VRRC:$vB))>; 689 690 def : Pat<(v16i8 (sra (v16i8 VRRC:$vA), (v16i8 VRRC:$vB))), 691 (v16i8 (VSRAB VRRC:$vA, VRRC:$vB))>; 692 def : Pat<(v8i16 (sra (v8i16 VRRC:$vA), (v8i16 VRRC:$vB))), 693 (v8i16 (VSRAH VRRC:$vA, VRRC:$vB))>; 694 def : Pat<(v4i32 (sra (v4i32 VRRC:$vA), (v4i32 VRRC:$vB))), 695 (v4i32 (VSRAW VRRC:$vA, VRRC:$vB))>; 696
