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      1 //===- SparcRegisterInfo.cpp - SPARC Register Information -------*- C++ -*-===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // This file contains the SPARC implementation of the TargetRegisterInfo class.
     11 //
     12 //===----------------------------------------------------------------------===//
     13 
     14 #include "Sparc.h"
     15 #include "SparcRegisterInfo.h"
     16 #include "SparcSubtarget.h"
     17 #include "llvm/CodeGen/MachineInstrBuilder.h"
     18 #include "llvm/CodeGen/MachineFunction.h"
     19 #include "llvm/CodeGen/MachineFrameInfo.h"
     20 #include "llvm/Support/ErrorHandling.h"
     21 #include "llvm/Target/TargetInstrInfo.h"
     22 #include "llvm/Type.h"
     23 #include "llvm/ADT/BitVector.h"
     24 #include "llvm/ADT/STLExtras.h"
     25 
     26 #define GET_REGINFO_TARGET_DESC
     27 #include "SparcGenRegisterInfo.inc"
     28 
     29 using namespace llvm;
     30 
     31 SparcRegisterInfo::SparcRegisterInfo(SparcSubtarget &st,
     32                                      const TargetInstrInfo &tii)
     33   : SparcGenRegisterInfo(SP::I7), Subtarget(st), TII(tii) {
     34 }
     35 
     36 const unsigned* SparcRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF)
     37                                                                          const {
     38   static const unsigned CalleeSavedRegs[] = { 0 };
     39   return CalleeSavedRegs;
     40 }
     41 
     42 BitVector SparcRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
     43   BitVector Reserved(getNumRegs());
     44   // FIXME: G1 reserved for now for large imm generation by frame code.
     45   Reserved.set(SP::G1);
     46   Reserved.set(SP::G2);
     47   Reserved.set(SP::G3);
     48   Reserved.set(SP::G4);
     49   Reserved.set(SP::O6);
     50   Reserved.set(SP::I6);
     51   Reserved.set(SP::I7);
     52   Reserved.set(SP::G0);
     53   Reserved.set(SP::G5);
     54   Reserved.set(SP::G6);
     55   Reserved.set(SP::G7);
     56   return Reserved;
     57 }
     58 
     59 void SparcRegisterInfo::
     60 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
     61                               MachineBasicBlock::iterator I) const {
     62   MachineInstr &MI = *I;
     63   DebugLoc dl = MI.getDebugLoc();
     64   int Size = MI.getOperand(0).getImm();
     65   if (MI.getOpcode() == SP::ADJCALLSTACKDOWN)
     66     Size = -Size;
     67   if (Size)
     68     BuildMI(MBB, I, dl, TII.get(SP::ADDri), SP::O6).addReg(SP::O6).addImm(Size);
     69   MBB.erase(I);
     70 }
     71 
     72 void
     73 SparcRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
     74                                        int SPAdj, RegScavenger *RS) const {
     75   assert(SPAdj == 0 && "Unexpected");
     76 
     77   unsigned i = 0;
     78   MachineInstr &MI = *II;
     79   DebugLoc dl = MI.getDebugLoc();
     80   while (!MI.getOperand(i).isFI()) {
     81     ++i;
     82     assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
     83   }
     84 
     85   int FrameIndex = MI.getOperand(i).getIndex();
     86 
     87   // Addressable stack objects are accessed using neg. offsets from %fp
     88   MachineFunction &MF = *MI.getParent()->getParent();
     89   int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
     90                MI.getOperand(i+1).getImm();
     91 
     92   // Replace frame index with a frame pointer reference.
     93   if (Offset >= -4096 && Offset <= 4095) {
     94     // If the offset is small enough to fit in the immediate field, directly
     95     // encode it.
     96     MI.getOperand(i).ChangeToRegister(SP::I6, false);
     97     MI.getOperand(i+1).ChangeToImmediate(Offset);
     98   } else {
     99     // Otherwise, emit a G1 = SETHI %hi(offset).  FIXME: it would be better to
    100     // scavenge a register here instead of reserving G1 all of the time.
    101     unsigned OffHi = (unsigned)Offset >> 10U;
    102     BuildMI(*MI.getParent(), II, dl, TII.get(SP::SETHIi), SP::G1).addImm(OffHi);
    103     // Emit G1 = G1 + I6
    104     BuildMI(*MI.getParent(), II, dl, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1)
    105       .addReg(SP::I6);
    106     // Insert: G1+%lo(offset) into the user.
    107     MI.getOperand(i).ChangeToRegister(SP::G1, false);
    108     MI.getOperand(i+1).ChangeToImmediate(Offset & ((1 << 10)-1));
    109   }
    110 }
    111 
    112 void SparcRegisterInfo::
    113 processFunctionBeforeFrameFinalized(MachineFunction &MF) const {}
    114 
    115 unsigned SparcRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
    116   return SP::I6;
    117 }
    118 
    119 unsigned SparcRegisterInfo::getEHExceptionRegister() const {
    120   llvm_unreachable("What is the exception register");
    121   return 0;
    122 }
    123 
    124 unsigned SparcRegisterInfo::getEHHandlerRegister() const {
    125   llvm_unreachable("What is the exception handler register");
    126   return 0;
    127 }
    128