1 //===-- SparcTargetMachine.cpp - Define TargetMachine for Sparc -----------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "Sparc.h" 14 #include "SparcTargetMachine.h" 15 #include "llvm/PassManager.h" 16 #include "llvm/Target/TargetRegistry.h" 17 using namespace llvm; 18 19 extern "C" void LLVMInitializeSparcTarget() { 20 // Register the target. 21 RegisterTargetMachine<SparcV8TargetMachine> X(TheSparcTarget); 22 RegisterTargetMachine<SparcV9TargetMachine> Y(TheSparcV9Target); 23 } 24 25 /// SparcTargetMachine ctor - Create an ILP32 architecture model 26 /// 27 SparcTargetMachine::SparcTargetMachine(const Target &T, StringRef TT, 28 StringRef CPU, StringRef FS, 29 Reloc::Model RM, bool is64bit) 30 : LLVMTargetMachine(T, TT, CPU, FS, RM), 31 Subtarget(TT, CPU, FS, is64bit), 32 DataLayout(Subtarget.getDataLayout()), 33 TLInfo(*this), TSInfo(*this), InstrInfo(Subtarget), 34 FrameLowering(Subtarget) { 35 } 36 37 bool SparcTargetMachine::addInstSelector(PassManagerBase &PM, 38 CodeGenOpt::Level OptLevel) { 39 PM.add(createSparcISelDag(*this)); 40 return false; 41 } 42 43 /// addPreEmitPass - This pass may be implemented by targets that want to run 44 /// passes immediately before machine code is emitted. This should return 45 /// true if -print-machineinstrs should print out the code after the passes. 46 bool SparcTargetMachine::addPreEmitPass(PassManagerBase &PM, 47 CodeGenOpt::Level OptLevel){ 48 PM.add(createSparcFPMoverPass(*this)); 49 PM.add(createSparcDelaySlotFillerPass(*this)); 50 return true; 51 } 52 53 SparcV8TargetMachine::SparcV8TargetMachine(const Target &T, 54 StringRef TT, 55 StringRef CPU, 56 StringRef FS, Reloc::Model RM) 57 : SparcTargetMachine(T, TT, CPU, FS, RM, false) { 58 } 59 60 SparcV9TargetMachine::SparcV9TargetMachine(const Target &T, 61 StringRef TT, 62 StringRef CPU, 63 StringRef FS, Reloc::Model RM) 64 : SparcTargetMachine(T, TT, CPU, FS, RM, true) { 65 } 66
