1 //===- X86InstrInfo.td - Main X86 Instruction Definition ---*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file describes the X86 instruction set, defining the instructions, and 11 // properties of the instructions which are needed for code generation, machine 12 // code emission, and analysis. 13 // 14 //===----------------------------------------------------------------------===// 15 16 //===----------------------------------------------------------------------===// 17 // X86 specific DAG Nodes. 18 // 19 20 def SDTIntShiftDOp: SDTypeProfile<1, 3, 21 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, 22 SDTCisInt<0>, SDTCisInt<3>]>; 23 24 def SDTX86CmpTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisSameAs<1, 2>]>; 25 26 def SDTX86Cmpsd : SDTypeProfile<1, 3, [SDTCisVT<0, f64>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>; 27 def SDTX86Cmpss : SDTypeProfile<1, 3, [SDTCisVT<0, f32>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>; 28 29 def SDTX86Cmov : SDTypeProfile<1, 4, 30 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, 31 SDTCisVT<3, i8>, SDTCisVT<4, i32>]>; 32 33 // Unary and binary operator instructions that set EFLAGS as a side-effect. 34 def SDTUnaryArithWithFlags : SDTypeProfile<2, 1, 35 [SDTCisInt<0>, SDTCisVT<1, i32>]>; 36 37 def SDTBinaryArithWithFlags : SDTypeProfile<2, 2, 38 [SDTCisSameAs<0, 2>, 39 SDTCisSameAs<0, 3>, 40 SDTCisInt<0>, SDTCisVT<1, i32>]>; 41 42 // SDTBinaryArithWithFlagsInOut - RES1, EFLAGS = op LHS, RHS, EFLAGS 43 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3, 44 [SDTCisSameAs<0, 2>, 45 SDTCisSameAs<0, 3>, 46 SDTCisInt<0>, 47 SDTCisVT<1, i32>, 48 SDTCisVT<4, i32>]>; 49 // RES1, RES2, FLAGS = op LHS, RHS 50 def SDT2ResultBinaryArithWithFlags : SDTypeProfile<3, 2, 51 [SDTCisSameAs<0, 1>, 52 SDTCisSameAs<0, 2>, 53 SDTCisSameAs<0, 3>, 54 SDTCisInt<0>, SDTCisVT<1, i32>]>; 55 def SDTX86BrCond : SDTypeProfile<0, 3, 56 [SDTCisVT<0, OtherVT>, 57 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>; 58 59 def SDTX86SetCC : SDTypeProfile<1, 2, 60 [SDTCisVT<0, i8>, 61 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>; 62 def SDTX86SetCC_C : SDTypeProfile<1, 2, 63 [SDTCisInt<0>, 64 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>; 65 66 def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>, 67 SDTCisVT<2, i8>]>; 68 def SDTX86cas8 : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>; 69 70 def SDTX86atomicBinary : SDTypeProfile<2, 3, [SDTCisInt<0>, SDTCisInt<1>, 71 SDTCisPtrTy<2>, SDTCisInt<3>,SDTCisInt<4>]>; 72 def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>; 73 74 def SDT_X86CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>; 75 def SDT_X86CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, 76 SDTCisVT<1, i32>]>; 77 78 def SDT_X86Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>; 79 80 def SDT_X86VASTART_SAVE_XMM_REGS : SDTypeProfile<0, -1, [SDTCisVT<0, i8>, 81 SDTCisVT<1, iPTR>, 82 SDTCisVT<2, iPTR>]>; 83 84 def SDT_X86VAARG_64 : SDTypeProfile<1, -1, [SDTCisPtrTy<0>, 85 SDTCisPtrTy<1>, 86 SDTCisVT<2, i32>, 87 SDTCisVT<3, i8>, 88 SDTCisVT<4, i32>]>; 89 90 def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>; 91 92 def SDTX86Void : SDTypeProfile<0, 0, []>; 93 94 def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>; 95 96 def SDT_X86TLSADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>; 97 98 def SDT_X86TLSCALL : SDTypeProfile<0, 1, [SDTCisInt<0>]>; 99 100 def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>; 101 102 def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>; 103 104 def SDT_X86MEMBARRIER : SDTypeProfile<0, 0, []>; 105 def SDT_X86MEMBARRIERNoSSE : SDTypeProfile<0, 1, [SDTCisInt<0>]>; 106 107 def X86MemBarrier : SDNode<"X86ISD::MEMBARRIER", SDT_X86MEMBARRIER, 108 [SDNPHasChain]>; 109 def X86MemBarrierNoSSE : SDNode<"X86ISD::MEMBARRIER", SDT_X86MEMBARRIERNoSSE, 110 [SDNPHasChain]>; 111 def X86MFence : SDNode<"X86ISD::MFENCE", SDT_X86MEMBARRIER, 112 [SDNPHasChain]>; 113 def X86SFence : SDNode<"X86ISD::SFENCE", SDT_X86MEMBARRIER, 114 [SDNPHasChain]>; 115 def X86LFence : SDNode<"X86ISD::LFENCE", SDT_X86MEMBARRIER, 116 [SDNPHasChain]>; 117 118 119 def X86bsf : SDNode<"X86ISD::BSF", SDTUnaryArithWithFlags>; 120 def X86bsr : SDNode<"X86ISD::BSR", SDTUnaryArithWithFlags>; 121 def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>; 122 def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>; 123 124 def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>; 125 def X86bt : SDNode<"X86ISD::BT", SDTX86CmpTest>; 126 127 def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>; 128 def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond, 129 [SDNPHasChain]>; 130 def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>; 131 def X86setcc_c : SDNode<"X86ISD::SETCC_CARRY", SDTX86SetCC_C>; 132 133 def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas, 134 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore, 135 SDNPMayLoad, SDNPMemOperand]>; 136 def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86cas8, 137 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore, 138 SDNPMayLoad, SDNPMemOperand]>; 139 def X86AtomAdd64 : SDNode<"X86ISD::ATOMADD64_DAG", SDTX86atomicBinary, 140 [SDNPHasChain, SDNPMayStore, 141 SDNPMayLoad, SDNPMemOperand]>; 142 def X86AtomSub64 : SDNode<"X86ISD::ATOMSUB64_DAG", SDTX86atomicBinary, 143 [SDNPHasChain, SDNPMayStore, 144 SDNPMayLoad, SDNPMemOperand]>; 145 def X86AtomOr64 : SDNode<"X86ISD::ATOMOR64_DAG", SDTX86atomicBinary, 146 [SDNPHasChain, SDNPMayStore, 147 SDNPMayLoad, SDNPMemOperand]>; 148 def X86AtomXor64 : SDNode<"X86ISD::ATOMXOR64_DAG", SDTX86atomicBinary, 149 [SDNPHasChain, SDNPMayStore, 150 SDNPMayLoad, SDNPMemOperand]>; 151 def X86AtomAnd64 : SDNode<"X86ISD::ATOMAND64_DAG", SDTX86atomicBinary, 152 [SDNPHasChain, SDNPMayStore, 153 SDNPMayLoad, SDNPMemOperand]>; 154 def X86AtomNand64 : SDNode<"X86ISD::ATOMNAND64_DAG", SDTX86atomicBinary, 155 [SDNPHasChain, SDNPMayStore, 156 SDNPMayLoad, SDNPMemOperand]>; 157 def X86AtomSwap64 : SDNode<"X86ISD::ATOMSWAP64_DAG", SDTX86atomicBinary, 158 [SDNPHasChain, SDNPMayStore, 159 SDNPMayLoad, SDNPMemOperand]>; 160 def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret, 161 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 162 163 def X86vastart_save_xmm_regs : 164 SDNode<"X86ISD::VASTART_SAVE_XMM_REGS", 165 SDT_X86VASTART_SAVE_XMM_REGS, 166 [SDNPHasChain, SDNPVariadic]>; 167 def X86vaarg64 : 168 SDNode<"X86ISD::VAARG_64", SDT_X86VAARG_64, 169 [SDNPHasChain, SDNPMayLoad, SDNPMayStore, 170 SDNPMemOperand]>; 171 def X86callseq_start : 172 SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart, 173 [SDNPHasChain, SDNPOutGlue]>; 174 def X86callseq_end : 175 SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd, 176 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 177 178 def X86call : SDNode<"X86ISD::CALL", SDT_X86Call, 179 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, 180 SDNPVariadic]>; 181 182 def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr, 183 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore]>; 184 def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr, 185 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore, 186 SDNPMayLoad]>; 187 188 def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG", SDTX86Void, 189 [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>; 190 191 def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>; 192 def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>; 193 194 def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR, 195 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 196 197 def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET, 198 [SDNPHasChain]>; 199 200 def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET, 201 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 202 203 def X86add_flag : SDNode<"X86ISD::ADD", SDTBinaryArithWithFlags, 204 [SDNPCommutative]>; 205 def X86sub_flag : SDNode<"X86ISD::SUB", SDTBinaryArithWithFlags>; 206 def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags, 207 [SDNPCommutative]>; 208 def X86umul_flag : SDNode<"X86ISD::UMUL", SDT2ResultBinaryArithWithFlags, 209 [SDNPCommutative]>; 210 def X86adc_flag : SDNode<"X86ISD::ADC", SDTBinaryArithWithFlagsInOut>; 211 def X86sbb_flag : SDNode<"X86ISD::SBB", SDTBinaryArithWithFlagsInOut>; 212 213 def X86inc_flag : SDNode<"X86ISD::INC", SDTUnaryArithWithFlags>; 214 def X86dec_flag : SDNode<"X86ISD::DEC", SDTUnaryArithWithFlags>; 215 def X86or_flag : SDNode<"X86ISD::OR", SDTBinaryArithWithFlags, 216 [SDNPCommutative]>; 217 def X86xor_flag : SDNode<"X86ISD::XOR", SDTBinaryArithWithFlags, 218 [SDNPCommutative]>; 219 def X86and_flag : SDNode<"X86ISD::AND", SDTBinaryArithWithFlags, 220 [SDNPCommutative]>; 221 222 def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>; 223 224 def X86WinAlloca : SDNode<"X86ISD::WIN_ALLOCA", SDTX86Void, 225 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>; 226 227 def X86TLSCall : SDNode<"X86ISD::TLSCALL", SDT_X86TLSCALL, 228 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 229 230 //===----------------------------------------------------------------------===// 231 // X86 Operand Definitions. 232 // 233 234 // A version of ptr_rc which excludes SP, ESP, and RSP. This is used for 235 // the index operand of an address, to conform to x86 encoding restrictions. 236 def ptr_rc_nosp : PointerLikeRegClass<1>; 237 238 // *mem - Operand definitions for the funky X86 addressing mode operands. 239 // 240 def X86MemAsmOperand : AsmOperandClass { 241 let Name = "Mem"; 242 let SuperClasses = []; 243 } 244 def X86AbsMemAsmOperand : AsmOperandClass { 245 let Name = "AbsMem"; 246 let SuperClasses = [X86MemAsmOperand]; 247 } 248 class X86MemOperand<string printMethod> : Operand<iPTR> { 249 let PrintMethod = printMethod; 250 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm); 251 let ParserMatchClass = X86MemAsmOperand; 252 } 253 254 let OperandType = "OPERAND_MEMORY" in { 255 def opaque32mem : X86MemOperand<"printopaquemem">; 256 def opaque48mem : X86MemOperand<"printopaquemem">; 257 def opaque80mem : X86MemOperand<"printopaquemem">; 258 def opaque512mem : X86MemOperand<"printopaquemem">; 259 260 def i8mem : X86MemOperand<"printi8mem">; 261 def i16mem : X86MemOperand<"printi16mem">; 262 def i32mem : X86MemOperand<"printi32mem">; 263 def i64mem : X86MemOperand<"printi64mem">; 264 def i128mem : X86MemOperand<"printi128mem">; 265 def i256mem : X86MemOperand<"printi256mem">; 266 def f32mem : X86MemOperand<"printf32mem">; 267 def f64mem : X86MemOperand<"printf64mem">; 268 def f80mem : X86MemOperand<"printf80mem">; 269 def f128mem : X86MemOperand<"printf128mem">; 270 def f256mem : X86MemOperand<"printf256mem">; 271 } 272 273 // A version of i8mem for use on x86-64 that uses GR64_NOREX instead of 274 // plain GR64, so that it doesn't potentially require a REX prefix. 275 def i8mem_NOREX : Operand<i64> { 276 let PrintMethod = "printi8mem"; 277 let MIOperandInfo = (ops GR64_NOREX, i8imm, GR64_NOREX_NOSP, i32imm, i8imm); 278 let ParserMatchClass = X86MemAsmOperand; 279 let OperandType = "OPERAND_MEMORY"; 280 } 281 282 // GPRs available for tailcall. 283 // It represents GR64_TC or GR64_TCW64. 284 def ptr_rc_tailcall : PointerLikeRegClass<2>; 285 286 // Special i32mem for addresses of load folding tail calls. These are not 287 // allowed to use callee-saved registers since they must be scheduled 288 // after callee-saved register are popped. 289 def i32mem_TC : Operand<i32> { 290 let PrintMethod = "printi32mem"; 291 let MIOperandInfo = (ops GR32_TC, i8imm, GR32_TC, i32imm, i8imm); 292 let ParserMatchClass = X86MemAsmOperand; 293 let OperandType = "OPERAND_MEMORY"; 294 } 295 296 // Special i64mem for addresses of load folding tail calls. These are not 297 // allowed to use callee-saved registers since they must be scheduled 298 // after callee-saved register are popped. 299 def i64mem_TC : Operand<i64> { 300 let PrintMethod = "printi64mem"; 301 let MIOperandInfo = (ops ptr_rc_tailcall, i8imm, 302 ptr_rc_tailcall, i32imm, i8imm); 303 let ParserMatchClass = X86MemAsmOperand; 304 let OperandType = "OPERAND_MEMORY"; 305 } 306 307 let OperandType = "OPERAND_PCREL", 308 ParserMatchClass = X86AbsMemAsmOperand, 309 PrintMethod = "print_pcrel_imm" in { 310 def i32imm_pcrel : Operand<i32>; 311 def i16imm_pcrel : Operand<i16>; 312 313 def offset8 : Operand<i64>; 314 def offset16 : Operand<i64>; 315 def offset32 : Operand<i64>; 316 def offset64 : Operand<i64>; 317 318 // Branch targets have OtherVT type and print as pc-relative values. 319 def brtarget : Operand<OtherVT>; 320 def brtarget8 : Operand<OtherVT>; 321 322 } 323 324 def SSECC : Operand<i8> { 325 let PrintMethod = "printSSECC"; 326 let OperandType = "OPERAND_IMMEDIATE"; 327 } 328 329 class ImmSExtAsmOperandClass : AsmOperandClass { 330 let SuperClasses = [ImmAsmOperand]; 331 let RenderMethod = "addImmOperands"; 332 } 333 334 // Sign-extended immediate classes. We don't need to define the full lattice 335 // here because there is no instruction with an ambiguity between ImmSExti64i32 336 // and ImmSExti32i8. 337 // 338 // The strange ranges come from the fact that the assembler always works with 339 // 64-bit immediates, but for a 16-bit target value we want to accept both "-1" 340 // (which will be a -1ULL), and "0xFF" (-1 in 16-bits). 341 342 // [0, 0x7FFFFFFF] | 343 // [0xFFFFFFFF80000000, 0xFFFFFFFFFFFFFFFF] 344 def ImmSExti64i32AsmOperand : ImmSExtAsmOperandClass { 345 let Name = "ImmSExti64i32"; 346 } 347 348 // [0, 0x0000007F] | [0x000000000000FF80, 0x000000000000FFFF] | 349 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF] 350 def ImmSExti16i8AsmOperand : ImmSExtAsmOperandClass { 351 let Name = "ImmSExti16i8"; 352 let SuperClasses = [ImmSExti64i32AsmOperand]; 353 } 354 355 // [0, 0x0000007F] | [0x00000000FFFFFF80, 0x00000000FFFFFFFF] | 356 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF] 357 def ImmSExti32i8AsmOperand : ImmSExtAsmOperandClass { 358 let Name = "ImmSExti32i8"; 359 } 360 361 // [0, 0x0000007F] | 362 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF] 363 def ImmSExti64i8AsmOperand : ImmSExtAsmOperandClass { 364 let Name = "ImmSExti64i8"; 365 let SuperClasses = [ImmSExti16i8AsmOperand, ImmSExti32i8AsmOperand, 366 ImmSExti64i32AsmOperand]; 367 } 368 369 // A couple of more descriptive operand definitions. 370 // 16-bits but only 8 bits are significant. 371 def i16i8imm : Operand<i16> { 372 let ParserMatchClass = ImmSExti16i8AsmOperand; 373 let OperandType = "OPERAND_IMMEDIATE"; 374 } 375 // 32-bits but only 8 bits are significant. 376 def i32i8imm : Operand<i32> { 377 let ParserMatchClass = ImmSExti32i8AsmOperand; 378 let OperandType = "OPERAND_IMMEDIATE"; 379 } 380 381 // 64-bits but only 32 bits are significant. 382 def i64i32imm : Operand<i64> { 383 let ParserMatchClass = ImmSExti64i32AsmOperand; 384 let OperandType = "OPERAND_IMMEDIATE"; 385 } 386 387 // 64-bits but only 32 bits are significant, and those bits are treated as being 388 // pc relative. 389 def i64i32imm_pcrel : Operand<i64> { 390 let PrintMethod = "print_pcrel_imm"; 391 let ParserMatchClass = X86AbsMemAsmOperand; 392 } 393 394 // 64-bits but only 8 bits are significant. 395 def i64i8imm : Operand<i64> { 396 let ParserMatchClass = ImmSExti64i8AsmOperand; 397 } 398 399 def lea64_32mem : Operand<i32> { 400 let PrintMethod = "printi32mem"; 401 let AsmOperandLowerMethod = "lower_lea64_32mem"; 402 let MIOperandInfo = (ops GR32, i8imm, GR32_NOSP, i32imm, i8imm); 403 let ParserMatchClass = X86MemAsmOperand; 404 } 405 406 407 //===----------------------------------------------------------------------===// 408 // X86 Complex Pattern Definitions. 409 // 410 411 // Define X86 specific addressing mode. 412 def addr : ComplexPattern<iPTR, 5, "SelectAddr", [], [SDNPWantParent]>; 413 def lea32addr : ComplexPattern<i32, 5, "SelectLEAAddr", 414 [add, sub, mul, X86mul_imm, shl, or, frameindex], 415 []>; 416 def tls32addr : ComplexPattern<i32, 5, "SelectTLSADDRAddr", 417 [tglobaltlsaddr], []>; 418 419 def lea64addr : ComplexPattern<i64, 5, "SelectLEAAddr", 420 [add, sub, mul, X86mul_imm, shl, or, frameindex, 421 X86WrapperRIP], []>; 422 423 def tls64addr : ComplexPattern<i64, 5, "SelectTLSADDRAddr", 424 [tglobaltlsaddr], []>; 425 426 //===----------------------------------------------------------------------===// 427 // X86 Instruction Predicate Definitions. 428 def HasCMov : Predicate<"Subtarget->hasCMov()">; 429 def NoCMov : Predicate<"!Subtarget->hasCMov()">; 430 431 def HasMMX : Predicate<"Subtarget->hasMMX()">; 432 def Has3DNow : Predicate<"Subtarget->has3DNow()">; 433 def Has3DNowA : Predicate<"Subtarget->has3DNowA()">; 434 def HasSSE1 : Predicate<"Subtarget->hasSSE1()">; 435 def HasSSE2 : Predicate<"Subtarget->hasSSE2()">; 436 def HasSSE3 : Predicate<"Subtarget->hasSSE3()">; 437 def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">; 438 def HasSSE41 : Predicate<"Subtarget->hasSSE41()">; 439 def HasSSE42 : Predicate<"Subtarget->hasSSE42()">; 440 def HasSSE4A : Predicate<"Subtarget->hasSSE4A()">; 441 442 def HasAVX : Predicate<"Subtarget->hasAVX()">; 443 def HasXMMInt : Predicate<"Subtarget->hasXMMInt()">; 444 445 def HasAES : Predicate<"Subtarget->hasAES()">; 446 def HasCLMUL : Predicate<"Subtarget->hasCLMUL()">; 447 def HasFMA3 : Predicate<"Subtarget->hasFMA3()">; 448 def HasFMA4 : Predicate<"Subtarget->hasFMA4()">; 449 def FPStackf32 : Predicate<"!Subtarget->hasXMM()">; 450 def FPStackf64 : Predicate<"!Subtarget->hasXMMInt()">; 451 def In32BitMode : Predicate<"!Subtarget->is64Bit()">, 452 AssemblerPredicate<"!Mode64Bit">; 453 def In64BitMode : Predicate<"Subtarget->is64Bit()">, 454 AssemblerPredicate<"Mode64Bit">; 455 def IsWin64 : Predicate<"Subtarget->isTargetWin64()">; 456 def NotWin64 : Predicate<"!Subtarget->isTargetWin64()">; 457 def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">; 458 def KernelCode : Predicate<"TM.getCodeModel() == CodeModel::Kernel">; 459 def FarData : Predicate<"TM.getCodeModel() != CodeModel::Small &&" 460 "TM.getCodeModel() != CodeModel::Kernel">; 461 def NearData : Predicate<"TM.getCodeModel() == CodeModel::Small ||" 462 "TM.getCodeModel() == CodeModel::Kernel">; 463 def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">; 464 def IsNotPIC : Predicate<"TM.getRelocationModel() != Reloc::PIC_">; 465 def OptForSize : Predicate<"OptForSize">; 466 def OptForSpeed : Predicate<"!OptForSize">; 467 def FastBTMem : Predicate<"!Subtarget->isBTMemSlow()">; 468 def CallImmAddr : Predicate<"Subtarget->IsLegalToCallImmediateAddr(TM)">; 469 470 //===----------------------------------------------------------------------===// 471 // X86 Instruction Format Definitions. 472 // 473 474 include "X86InstrFormats.td" 475 476 //===----------------------------------------------------------------------===// 477 // Pattern fragments. 478 // 479 480 // X86 specific condition code. These correspond to CondCode in 481 // X86InstrInfo.h. They must be kept in synch. 482 def X86_COND_A : PatLeaf<(i8 0)>; // alt. COND_NBE 483 def X86_COND_AE : PatLeaf<(i8 1)>; // alt. COND_NC 484 def X86_COND_B : PatLeaf<(i8 2)>; // alt. COND_C 485 def X86_COND_BE : PatLeaf<(i8 3)>; // alt. COND_NA 486 def X86_COND_E : PatLeaf<(i8 4)>; // alt. COND_Z 487 def X86_COND_G : PatLeaf<(i8 5)>; // alt. COND_NLE 488 def X86_COND_GE : PatLeaf<(i8 6)>; // alt. COND_NL 489 def X86_COND_L : PatLeaf<(i8 7)>; // alt. COND_NGE 490 def X86_COND_LE : PatLeaf<(i8 8)>; // alt. COND_NG 491 def X86_COND_NE : PatLeaf<(i8 9)>; // alt. COND_NZ 492 def X86_COND_NO : PatLeaf<(i8 10)>; 493 def X86_COND_NP : PatLeaf<(i8 11)>; // alt. COND_PO 494 def X86_COND_NS : PatLeaf<(i8 12)>; 495 def X86_COND_O : PatLeaf<(i8 13)>; 496 def X86_COND_P : PatLeaf<(i8 14)>; // alt. COND_PE 497 def X86_COND_S : PatLeaf<(i8 15)>; 498 499 let FastIselShouldIgnore = 1 in { // FastIsel should ignore all simm8 instrs. 500 def i16immSExt8 : ImmLeaf<i16, [{ return Imm == (int8_t)Imm; }]>; 501 def i32immSExt8 : ImmLeaf<i32, [{ return Imm == (int8_t)Imm; }]>; 502 def i64immSExt8 : ImmLeaf<i64, [{ return Imm == (int8_t)Imm; }]>; 503 } 504 505 def i64immSExt32 : ImmLeaf<i64, [{ return Imm == (int32_t)Imm; }]>; 506 507 508 // i64immZExt32 predicate - True if the 64-bit immediate fits in a 32-bit 509 // unsigned field. 510 def i64immZExt32 : ImmLeaf<i64, [{ return (uint64_t)Imm == (uint32_t)Imm; }]>; 511 512 def i64immZExt32SExt8 : ImmLeaf<i64, [{ 513 return (uint64_t)Imm == (uint32_t)Imm && (int32_t)Imm == (int8_t)Imm; 514 }]>; 515 516 // Helper fragments for loads. 517 // It's always safe to treat a anyext i16 load as a i32 load if the i16 is 518 // known to be 32-bit aligned or better. Ditto for i8 to i16. 519 def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{ 520 LoadSDNode *LD = cast<LoadSDNode>(N); 521 ISD::LoadExtType ExtType = LD->getExtensionType(); 522 if (ExtType == ISD::NON_EXTLOAD) 523 return true; 524 if (ExtType == ISD::EXTLOAD) 525 return LD->getAlignment() >= 2 && !LD->isVolatile(); 526 return false; 527 }]>; 528 529 def loadi16_anyext : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)),[{ 530 LoadSDNode *LD = cast<LoadSDNode>(N); 531 ISD::LoadExtType ExtType = LD->getExtensionType(); 532 if (ExtType == ISD::EXTLOAD) 533 return LD->getAlignment() >= 2 && !LD->isVolatile(); 534 return false; 535 }]>; 536 537 def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{ 538 LoadSDNode *LD = cast<LoadSDNode>(N); 539 ISD::LoadExtType ExtType = LD->getExtensionType(); 540 if (ExtType == ISD::NON_EXTLOAD) 541 return true; 542 if (ExtType == ISD::EXTLOAD) 543 return LD->getAlignment() >= 4 && !LD->isVolatile(); 544 return false; 545 }]>; 546 547 def loadi8 : PatFrag<(ops node:$ptr), (i8 (load node:$ptr))>; 548 def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr))>; 549 def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr))>; 550 def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr))>; 551 def loadf80 : PatFrag<(ops node:$ptr), (f80 (load node:$ptr))>; 552 553 def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>; 554 def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>; 555 def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>; 556 def sextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (sextloadi8 node:$ptr))>; 557 def sextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (sextloadi16 node:$ptr))>; 558 def sextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (sextloadi32 node:$ptr))>; 559 560 def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>; 561 def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>; 562 def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>; 563 def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>; 564 def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>; 565 def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>; 566 def zextloadi64i1 : PatFrag<(ops node:$ptr), (i64 (zextloadi1 node:$ptr))>; 567 def zextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (zextloadi8 node:$ptr))>; 568 def zextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (zextloadi16 node:$ptr))>; 569 def zextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (zextloadi32 node:$ptr))>; 570 571 def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>; 572 def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>; 573 def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>; 574 def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>; 575 def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>; 576 def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>; 577 def extloadi64i1 : PatFrag<(ops node:$ptr), (i64 (extloadi1 node:$ptr))>; 578 def extloadi64i8 : PatFrag<(ops node:$ptr), (i64 (extloadi8 node:$ptr))>; 579 def extloadi64i16 : PatFrag<(ops node:$ptr), (i64 (extloadi16 node:$ptr))>; 580 def extloadi64i32 : PatFrag<(ops node:$ptr), (i64 (extloadi32 node:$ptr))>; 581 582 583 // An 'and' node with a single use. 584 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{ 585 return N->hasOneUse(); 586 }]>; 587 // An 'srl' node with a single use. 588 def srl_su : PatFrag<(ops node:$lhs, node:$rhs), (srl node:$lhs, node:$rhs), [{ 589 return N->hasOneUse(); 590 }]>; 591 // An 'trunc' node with a single use. 592 def trunc_su : PatFrag<(ops node:$src), (trunc node:$src), [{ 593 return N->hasOneUse(); 594 }]>; 595 596 //===----------------------------------------------------------------------===// 597 // Instruction list. 598 // 599 600 // Nop 601 let neverHasSideEffects = 1 in { 602 def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", []>; 603 def NOOPW : I<0x1f, MRM0m, (outs), (ins i16mem:$zero), 604 "nop{w}\t$zero", []>, TB, OpSize; 605 def NOOPL : I<0x1f, MRM0m, (outs), (ins i32mem:$zero), 606 "nop{l}\t$zero", []>, TB; 607 } 608 609 610 // Constructing a stack frame. 611 def ENTER : Ii16<0xC8, RawFrmImm8, (outs), (ins i16imm:$len, i8imm:$lvl), 612 "enter\t$len, $lvl", []>; 613 614 let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, neverHasSideEffects=1 in 615 def LEAVE : I<0xC9, RawFrm, 616 (outs), (ins), "leave", []>, Requires<[In32BitMode]>; 617 618 let Defs = [RBP,RSP], Uses = [RBP,RSP], mayLoad = 1, neverHasSideEffects = 1 in 619 def LEAVE64 : I<0xC9, RawFrm, 620 (outs), (ins), "leave", []>, Requires<[In64BitMode]>; 621 622 //===----------------------------------------------------------------------===// 623 // Miscellaneous Instructions. 624 // 625 626 let Defs = [ESP], Uses = [ESP], neverHasSideEffects=1 in { 627 let mayLoad = 1 in { 628 def POP16r : I<0x58, AddRegFrm, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>, 629 OpSize; 630 def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>; 631 def POP16rmr: I<0x8F, MRM0r, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>, 632 OpSize; 633 def POP16rmm: I<0x8F, MRM0m, (outs i16mem:$dst), (ins), "pop{w}\t$dst", []>, 634 OpSize; 635 def POP32rmr: I<0x8F, MRM0r, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>; 636 def POP32rmm: I<0x8F, MRM0m, (outs i32mem:$dst), (ins), "pop{l}\t$dst", []>; 637 638 def POPF16 : I<0x9D, RawFrm, (outs), (ins), "popf{w}", []>, OpSize; 639 def POPF32 : I<0x9D, RawFrm, (outs), (ins), "popf{l|d}", []>, 640 Requires<[In32BitMode]>; 641 } 642 643 let mayStore = 1 in { 644 def PUSH16r : I<0x50, AddRegFrm, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>, 645 OpSize; 646 def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>; 647 def PUSH16rmr: I<0xFF, MRM6r, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>, 648 OpSize; 649 def PUSH16rmm: I<0xFF, MRM6m, (outs), (ins i16mem:$src), "push{w}\t$src",[]>, 650 OpSize; 651 def PUSH32rmr: I<0xFF, MRM6r, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>; 652 def PUSH32rmm: I<0xFF, MRM6m, (outs), (ins i32mem:$src), "push{l}\t$src",[]>; 653 654 def PUSHi8 : Ii8<0x6a, RawFrm, (outs), (ins i32i8imm:$imm), 655 "push{l}\t$imm", []>; 656 def PUSHi16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm), 657 "push{w}\t$imm", []>, OpSize; 658 def PUSHi32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm), 659 "push{l}\t$imm", []>; 660 661 def PUSHF16 : I<0x9C, RawFrm, (outs), (ins), "pushf{w}", []>, OpSize; 662 def PUSHF32 : I<0x9C, RawFrm, (outs), (ins), "pushf{l|d}", []>, 663 Requires<[In32BitMode]>; 664 665 } 666 } 667 668 let Defs = [RSP], Uses = [RSP], neverHasSideEffects=1 in { 669 let mayLoad = 1 in { 670 def POP64r : I<0x58, AddRegFrm, 671 (outs GR64:$reg), (ins), "pop{q}\t$reg", []>; 672 def POP64rmr: I<0x8F, MRM0r, (outs GR64:$reg), (ins), "pop{q}\t$reg", []>; 673 def POP64rmm: I<0x8F, MRM0m, (outs i64mem:$dst), (ins), "pop{q}\t$dst", []>; 674 } 675 let mayStore = 1 in { 676 def PUSH64r : I<0x50, AddRegFrm, 677 (outs), (ins GR64:$reg), "push{q}\t$reg", []>; 678 def PUSH64rmr: I<0xFF, MRM6r, (outs), (ins GR64:$reg), "push{q}\t$reg", []>; 679 def PUSH64rmm: I<0xFF, MRM6m, (outs), (ins i64mem:$src), "push{q}\t$src", []>; 680 } 681 } 682 683 let Defs = [RSP], Uses = [RSP], neverHasSideEffects = 1, mayStore = 1 in { 684 def PUSH64i8 : Ii8<0x6a, RawFrm, (outs), (ins i64i8imm:$imm), 685 "push{q}\t$imm", []>; 686 def PUSH64i16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm), 687 "push{q}\t$imm", []>; 688 def PUSH64i32 : Ii32<0x68, RawFrm, (outs), (ins i64i32imm:$imm), 689 "push{q}\t$imm", []>; 690 } 691 692 let Defs = [RSP, EFLAGS], Uses = [RSP], mayLoad = 1, neverHasSideEffects=1 in 693 def POPF64 : I<0x9D, RawFrm, (outs), (ins), "popfq", []>, 694 Requires<[In64BitMode]>; 695 let Defs = [RSP], Uses = [RSP, EFLAGS], mayStore = 1, neverHasSideEffects=1 in 696 def PUSHF64 : I<0x9C, RawFrm, (outs), (ins), "pushfq", []>, 697 Requires<[In64BitMode]>; 698 699 700 701 let Defs = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP], Uses = [ESP], 702 mayLoad=1, neverHasSideEffects=1 in { 703 def POPA32 : I<0x61, RawFrm, (outs), (ins), "popa{l}", []>, 704 Requires<[In32BitMode]>; 705 } 706 let Defs = [ESP], Uses = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP], 707 mayStore=1, neverHasSideEffects=1 in { 708 def PUSHA32 : I<0x60, RawFrm, (outs), (ins), "pusha{l}", []>, 709 Requires<[In32BitMode]>; 710 } 711 712 let Constraints = "$src = $dst" in { // GR32 = bswap GR32 713 def BSWAP32r : I<0xC8, AddRegFrm, 714 (outs GR32:$dst), (ins GR32:$src), 715 "bswap{l}\t$dst", 716 [(set GR32:$dst, (bswap GR32:$src))]>, TB; 717 718 def BSWAP64r : RI<0xC8, AddRegFrm, (outs GR64:$dst), (ins GR64:$src), 719 "bswap{q}\t$dst", 720 [(set GR64:$dst, (bswap GR64:$src))]>, TB; 721 } // Constraints = "$src = $dst" 722 723 // Bit scan instructions. 724 let Defs = [EFLAGS] in { 725 def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), 726 "bsf{w}\t{$src, $dst|$dst, $src}", 727 [(set GR16:$dst, EFLAGS, (X86bsf GR16:$src))]>, TB, OpSize; 728 def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), 729 "bsf{w}\t{$src, $dst|$dst, $src}", 730 [(set GR16:$dst, EFLAGS, (X86bsf (loadi16 addr:$src)))]>, TB, 731 OpSize; 732 def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), 733 "bsf{l}\t{$src, $dst|$dst, $src}", 734 [(set GR32:$dst, EFLAGS, (X86bsf GR32:$src))]>, TB; 735 def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), 736 "bsf{l}\t{$src, $dst|$dst, $src}", 737 [(set GR32:$dst, EFLAGS, (X86bsf (loadi32 addr:$src)))]>, TB; 738 def BSF64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), 739 "bsf{q}\t{$src, $dst|$dst, $src}", 740 [(set GR64:$dst, EFLAGS, (X86bsf GR64:$src))]>, TB; 741 def BSF64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), 742 "bsf{q}\t{$src, $dst|$dst, $src}", 743 [(set GR64:$dst, EFLAGS, (X86bsf (loadi64 addr:$src)))]>, TB; 744 745 def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), 746 "bsr{w}\t{$src, $dst|$dst, $src}", 747 [(set GR16:$dst, EFLAGS, (X86bsr GR16:$src))]>, TB, OpSize; 748 def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), 749 "bsr{w}\t{$src, $dst|$dst, $src}", 750 [(set GR16:$dst, EFLAGS, (X86bsr (loadi16 addr:$src)))]>, TB, 751 OpSize; 752 def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), 753 "bsr{l}\t{$src, $dst|$dst, $src}", 754 [(set GR32:$dst, EFLAGS, (X86bsr GR32:$src))]>, TB; 755 def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), 756 "bsr{l}\t{$src, $dst|$dst, $src}", 757 [(set GR32:$dst, EFLAGS, (X86bsr (loadi32 addr:$src)))]>, TB; 758 def BSR64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), 759 "bsr{q}\t{$src, $dst|$dst, $src}", 760 [(set GR64:$dst, EFLAGS, (X86bsr GR64:$src))]>, TB; 761 def BSR64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), 762 "bsr{q}\t{$src, $dst|$dst, $src}", 763 [(set GR64:$dst, EFLAGS, (X86bsr (loadi64 addr:$src)))]>, TB; 764 } // Defs = [EFLAGS] 765 766 767 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI 768 let Defs = [EDI,ESI], Uses = [EDI,ESI,EFLAGS] in { 769 def MOVSB : I<0xA4, RawFrm, (outs), (ins), "{movsb}", []>; 770 def MOVSW : I<0xA5, RawFrm, (outs), (ins), "{movsw}", []>, OpSize; 771 def MOVSD : I<0xA5, RawFrm, (outs), (ins), "{movsl|movsd}", []>; 772 def MOVSQ : RI<0xA5, RawFrm, (outs), (ins), "movsq", []>; 773 } 774 775 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI 776 let Defs = [EDI], Uses = [AL,EDI,EFLAGS] in 777 def STOSB : I<0xAA, RawFrm, (outs), (ins), "{stosb}", []>; 778 let Defs = [EDI], Uses = [AX,EDI,EFLAGS] in 779 def STOSW : I<0xAB, RawFrm, (outs), (ins), "{stosw}", []>, OpSize; 780 let Defs = [EDI], Uses = [EAX,EDI,EFLAGS] in 781 def STOSD : I<0xAB, RawFrm, (outs), (ins), "{stosl|stosd}", []>; 782 let Defs = [RCX,RDI], Uses = [RAX,RCX,RDI,EFLAGS] in 783 def STOSQ : RI<0xAB, RawFrm, (outs), (ins), "stosq", []>; 784 785 def SCAS8 : I<0xAE, RawFrm, (outs), (ins), "scas{b}", []>; 786 def SCAS16 : I<0xAF, RawFrm, (outs), (ins), "scas{w}", []>, OpSize; 787 def SCAS32 : I<0xAF, RawFrm, (outs), (ins), "scas{l}", []>; 788 def SCAS64 : RI<0xAF, RawFrm, (outs), (ins), "scasq", []>; 789 790 def CMPS8 : I<0xA6, RawFrm, (outs), (ins), "cmps{b}", []>; 791 def CMPS16 : I<0xA7, RawFrm, (outs), (ins), "cmps{w}", []>, OpSize; 792 def CMPS32 : I<0xA7, RawFrm, (outs), (ins), "cmps{l}", []>; 793 def CMPS64 : RI<0xA7, RawFrm, (outs), (ins), "cmpsq", []>; 794 795 796 //===----------------------------------------------------------------------===// 797 // Move Instructions. 798 // 799 800 let neverHasSideEffects = 1 in { 801 def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src), 802 "mov{b}\t{$src, $dst|$dst, $src}", []>; 803 def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src), 804 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize; 805 def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src), 806 "mov{l}\t{$src, $dst|$dst, $src}", []>; 807 def MOV64rr : RI<0x89, MRMDestReg, (outs GR64:$dst), (ins GR64:$src), 808 "mov{q}\t{$src, $dst|$dst, $src}", []>; 809 } 810 let isReMaterializable = 1, isAsCheapAsAMove = 1 in { 811 def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src), 812 "mov{b}\t{$src, $dst|$dst, $src}", 813 [(set GR8:$dst, imm:$src)]>; 814 def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src), 815 "mov{w}\t{$src, $dst|$dst, $src}", 816 [(set GR16:$dst, imm:$src)]>, OpSize; 817 def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src), 818 "mov{l}\t{$src, $dst|$dst, $src}", 819 [(set GR32:$dst, imm:$src)]>; 820 def MOV64ri : RIi64<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64imm:$src), 821 "movabs{q}\t{$src, $dst|$dst, $src}", 822 [(set GR64:$dst, imm:$src)]>; 823 def MOV64ri32 : RIi32<0xC7, MRM0r, (outs GR64:$dst), (ins i64i32imm:$src), 824 "mov{q}\t{$src, $dst|$dst, $src}", 825 [(set GR64:$dst, i64immSExt32:$src)]>; 826 } 827 828 def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src), 829 "mov{b}\t{$src, $dst|$dst, $src}", 830 [(store (i8 imm:$src), addr:$dst)]>; 831 def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src), 832 "mov{w}\t{$src, $dst|$dst, $src}", 833 [(store (i16 imm:$src), addr:$dst)]>, OpSize; 834 def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src), 835 "mov{l}\t{$src, $dst|$dst, $src}", 836 [(store (i32 imm:$src), addr:$dst)]>; 837 def MOV64mi32 : RIi32<0xC7, MRM0m, (outs), (ins i64mem:$dst, i64i32imm:$src), 838 "mov{q}\t{$src, $dst|$dst, $src}", 839 [(store i64immSExt32:$src, addr:$dst)]>; 840 841 /// moffs8, moffs16 and moffs32 versions of moves. The immediate is a 842 /// 32-bit offset from the PC. These are only valid in x86-32 mode. 843 def MOV8o8a : Ii32 <0xA0, RawFrm, (outs), (ins offset8:$src), 844 "mov{b}\t{$src, %al|%al, $src}", []>, 845 Requires<[In32BitMode]>; 846 def MOV16o16a : Ii32 <0xA1, RawFrm, (outs), (ins offset16:$src), 847 "mov{w}\t{$src, %ax|%ax, $src}", []>, OpSize, 848 Requires<[In32BitMode]>; 849 def MOV32o32a : Ii32 <0xA1, RawFrm, (outs), (ins offset32:$src), 850 "mov{l}\t{$src, %eax|%eax, $src}", []>, 851 Requires<[In32BitMode]>; 852 def MOV8ao8 : Ii32 <0xA2, RawFrm, (outs offset8:$dst), (ins), 853 "mov{b}\t{%al, $dst|$dst, %al}", []>, 854 Requires<[In32BitMode]>; 855 def MOV16ao16 : Ii32 <0xA3, RawFrm, (outs offset16:$dst), (ins), 856 "mov{w}\t{%ax, $dst|$dst, %ax}", []>, OpSize, 857 Requires<[In32BitMode]>; 858 def MOV32ao32 : Ii32 <0xA3, RawFrm, (outs offset32:$dst), (ins), 859 "mov{l}\t{%eax, $dst|$dst, %eax}", []>, 860 Requires<[In32BitMode]>; 861 862 // FIXME: These definitions are utterly broken 863 // Just leave them commented out for now because they're useless outside 864 // of the large code model, and most compilers won't generate the instructions 865 // in question. 866 /* 867 def MOV64o8a : RIi8<0xA0, RawFrm, (outs), (ins offset8:$src), 868 "mov{q}\t{$src, %rax|%rax, $src}", []>; 869 def MOV64o64a : RIi32<0xA1, RawFrm, (outs), (ins offset64:$src), 870 "mov{q}\t{$src, %rax|%rax, $src}", []>; 871 def MOV64ao8 : RIi8<0xA2, RawFrm, (outs offset8:$dst), (ins), 872 "mov{q}\t{%rax, $dst|$dst, %rax}", []>; 873 def MOV64ao64 : RIi32<0xA3, RawFrm, (outs offset64:$dst), (ins), 874 "mov{q}\t{%rax, $dst|$dst, %rax}", []>; 875 */ 876 877 878 let isCodeGenOnly = 1 in { 879 def MOV8rr_REV : I<0x8A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src), 880 "mov{b}\t{$src, $dst|$dst, $src}", []>; 881 def MOV16rr_REV : I<0x8B, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), 882 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize; 883 def MOV32rr_REV : I<0x8B, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), 884 "mov{l}\t{$src, $dst|$dst, $src}", []>; 885 def MOV64rr_REV : RI<0x8B, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), 886 "mov{q}\t{$src, $dst|$dst, $src}", []>; 887 } 888 889 let canFoldAsLoad = 1, isReMaterializable = 1 in { 890 def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src), 891 "mov{b}\t{$src, $dst|$dst, $src}", 892 [(set GR8:$dst, (loadi8 addr:$src))]>; 893 def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), 894 "mov{w}\t{$src, $dst|$dst, $src}", 895 [(set GR16:$dst, (loadi16 addr:$src))]>, OpSize; 896 def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), 897 "mov{l}\t{$src, $dst|$dst, $src}", 898 [(set GR32:$dst, (loadi32 addr:$src))]>; 899 def MOV64rm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), 900 "mov{q}\t{$src, $dst|$dst, $src}", 901 [(set GR64:$dst, (load addr:$src))]>; 902 } 903 904 def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src), 905 "mov{b}\t{$src, $dst|$dst, $src}", 906 [(store GR8:$src, addr:$dst)]>; 907 def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src), 908 "mov{w}\t{$src, $dst|$dst, $src}", 909 [(store GR16:$src, addr:$dst)]>, OpSize; 910 def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), 911 "mov{l}\t{$src, $dst|$dst, $src}", 912 [(store GR32:$src, addr:$dst)]>; 913 def MOV64mr : RI<0x89, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src), 914 "mov{q}\t{$src, $dst|$dst, $src}", 915 [(store GR64:$src, addr:$dst)]>; 916 917 // Versions of MOV8rr, MOV8mr, and MOV8rm that use i8mem_NOREX and GR8_NOREX so 918 // that they can be used for copying and storing h registers, which can't be 919 // encoded when a REX prefix is present. 920 let isCodeGenOnly = 1 in { 921 let neverHasSideEffects = 1 in 922 def MOV8rr_NOREX : I<0x88, MRMDestReg, 923 (outs GR8_NOREX:$dst), (ins GR8_NOREX:$src), 924 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>; 925 let mayStore = 1 in 926 def MOV8mr_NOREX : I<0x88, MRMDestMem, 927 (outs), (ins i8mem_NOREX:$dst, GR8_NOREX:$src), 928 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>; 929 let mayLoad = 1, 930 canFoldAsLoad = 1, isReMaterializable = 1 in 931 def MOV8rm_NOREX : I<0x8A, MRMSrcMem, 932 (outs GR8_NOREX:$dst), (ins i8mem_NOREX:$src), 933 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>; 934 } 935 936 937 // Condition code ops, incl. set if equal/not equal/... 938 let Defs = [EFLAGS], Uses = [AH], neverHasSideEffects = 1 in 939 def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf", []>; // flags = AH 940 let Defs = [AH], Uses = [EFLAGS], neverHasSideEffects = 1 in 941 def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", []>; // AH = flags 942 943 944 //===----------------------------------------------------------------------===// 945 // Bit tests instructions: BT, BTS, BTR, BTC. 946 947 let Defs = [EFLAGS] in { 948 def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2), 949 "bt{w}\t{$src2, $src1|$src1, $src2}", 950 [(set EFLAGS, (X86bt GR16:$src1, GR16:$src2))]>, OpSize, TB; 951 def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2), 952 "bt{l}\t{$src2, $src1|$src1, $src2}", 953 [(set EFLAGS, (X86bt GR32:$src1, GR32:$src2))]>, TB; 954 def BT64rr : RI<0xA3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2), 955 "bt{q}\t{$src2, $src1|$src1, $src2}", 956 [(set EFLAGS, (X86bt GR64:$src1, GR64:$src2))]>, TB; 957 958 // Unlike with the register+register form, the memory+register form of the 959 // bt instruction does not ignore the high bits of the index. From ISel's 960 // perspective, this is pretty bizarre. Make these instructions disassembly 961 // only for now. 962 963 def BT16mr : I<0xA3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2), 964 "bt{w}\t{$src2, $src1|$src1, $src2}", 965 // [(X86bt (loadi16 addr:$src1), GR16:$src2), 966 // (implicit EFLAGS)] 967 [] 968 >, OpSize, TB, Requires<[FastBTMem]>; 969 def BT32mr : I<0xA3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2), 970 "bt{l}\t{$src2, $src1|$src1, $src2}", 971 // [(X86bt (loadi32 addr:$src1), GR32:$src2), 972 // (implicit EFLAGS)] 973 [] 974 >, TB, Requires<[FastBTMem]>; 975 def BT64mr : RI<0xA3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2), 976 "bt{q}\t{$src2, $src1|$src1, $src2}", 977 // [(X86bt (loadi64 addr:$src1), GR64:$src2), 978 // (implicit EFLAGS)] 979 [] 980 >, TB; 981 982 def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR16:$src1, i16i8imm:$src2), 983 "bt{w}\t{$src2, $src1|$src1, $src2}", 984 [(set EFLAGS, (X86bt GR16:$src1, i16immSExt8:$src2))]>, 985 OpSize, TB; 986 def BT32ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR32:$src1, i32i8imm:$src2), 987 "bt{l}\t{$src2, $src1|$src1, $src2}", 988 [(set EFLAGS, (X86bt GR32:$src1, i32immSExt8:$src2))]>, TB; 989 def BT64ri8 : RIi8<0xBA, MRM4r, (outs), (ins GR64:$src1, i64i8imm:$src2), 990 "bt{q}\t{$src2, $src1|$src1, $src2}", 991 [(set EFLAGS, (X86bt GR64:$src1, i64immSExt8:$src2))]>, TB; 992 993 // Note that these instructions don't need FastBTMem because that 994 // only applies when the other operand is in a register. When it's 995 // an immediate, bt is still fast. 996 def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins i16mem:$src1, i16i8imm:$src2), 997 "bt{w}\t{$src2, $src1|$src1, $src2}", 998 [(set EFLAGS, (X86bt (loadi16 addr:$src1), i16immSExt8:$src2)) 999 ]>, OpSize, TB; 1000 def BT32mi8 : Ii8<0xBA, MRM4m, (outs), (ins i32mem:$src1, i32i8imm:$src2), 1001 "bt{l}\t{$src2, $src1|$src1, $src2}", 1002 [(set EFLAGS, (X86bt (loadi32 addr:$src1), i32immSExt8:$src2)) 1003 ]>, TB; 1004 def BT64mi8 : RIi8<0xBA, MRM4m, (outs), (ins i64mem:$src1, i64i8imm:$src2), 1005 "bt{q}\t{$src2, $src1|$src1, $src2}", 1006 [(set EFLAGS, (X86bt (loadi64 addr:$src1), 1007 i64immSExt8:$src2))]>, TB; 1008 1009 1010 def BTC16rr : I<0xBB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2), 1011 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB; 1012 def BTC32rr : I<0xBB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2), 1013 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB; 1014 def BTC64rr : RI<0xBB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2), 1015 "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB; 1016 def BTC16mr : I<0xBB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2), 1017 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB; 1018 def BTC32mr : I<0xBB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2), 1019 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB; 1020 def BTC64mr : RI<0xBB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2), 1021 "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB; 1022 def BTC16ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR16:$src1, i16i8imm:$src2), 1023 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB; 1024 def BTC32ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR32:$src1, i32i8imm:$src2), 1025 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB; 1026 def BTC64ri8 : RIi8<0xBA, MRM7r, (outs), (ins GR64:$src1, i64i8imm:$src2), 1027 "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB; 1028 def BTC16mi8 : Ii8<0xBA, MRM7m, (outs), (ins i16mem:$src1, i16i8imm:$src2), 1029 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB; 1030 def BTC32mi8 : Ii8<0xBA, MRM7m, (outs), (ins i32mem:$src1, i32i8imm:$src2), 1031 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB; 1032 def BTC64mi8 : RIi8<0xBA, MRM7m, (outs), (ins i64mem:$src1, i64i8imm:$src2), 1033 "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB; 1034 1035 def BTR16rr : I<0xB3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2), 1036 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB; 1037 def BTR32rr : I<0xB3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2), 1038 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB; 1039 def BTR64rr : RI<0xB3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2), 1040 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB; 1041 def BTR16mr : I<0xB3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2), 1042 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB; 1043 def BTR32mr : I<0xB3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2), 1044 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB; 1045 def BTR64mr : RI<0xB3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2), 1046 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB; 1047 def BTR16ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR16:$src1, i16i8imm:$src2), 1048 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB; 1049 def BTR32ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR32:$src1, i32i8imm:$src2), 1050 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB; 1051 def BTR64ri8 : RIi8<0xBA, MRM6r, (outs), (ins GR64:$src1, i64i8imm:$src2), 1052 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB; 1053 def BTR16mi8 : Ii8<0xBA, MRM6m, (outs), (ins i16mem:$src1, i16i8imm:$src2), 1054 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB; 1055 def BTR32mi8 : Ii8<0xBA, MRM6m, (outs), (ins i32mem:$src1, i32i8imm:$src2), 1056 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB; 1057 def BTR64mi8 : RIi8<0xBA, MRM6m, (outs), (ins i64mem:$src1, i64i8imm:$src2), 1058 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB; 1059 1060 def BTS16rr : I<0xAB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2), 1061 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB; 1062 def BTS32rr : I<0xAB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2), 1063 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB; 1064 def BTS64rr : RI<0xAB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2), 1065 "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB; 1066 def BTS16mr : I<0xAB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2), 1067 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB; 1068 def BTS32mr : I<0xAB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2), 1069 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB; 1070 def BTS64mr : RI<0xAB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2), 1071 "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB; 1072 def BTS16ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR16:$src1, i16i8imm:$src2), 1073 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB; 1074 def BTS32ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR32:$src1, i32i8imm:$src2), 1075 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB; 1076 def BTS64ri8 : RIi8<0xBA, MRM5r, (outs), (ins GR64:$src1, i64i8imm:$src2), 1077 "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB; 1078 def BTS16mi8 : Ii8<0xBA, MRM5m, (outs), (ins i16mem:$src1, i16i8imm:$src2), 1079 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB; 1080 def BTS32mi8 : Ii8<0xBA, MRM5m, (outs), (ins i32mem:$src1, i32i8imm:$src2), 1081 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB; 1082 def BTS64mi8 : RIi8<0xBA, MRM5m, (outs), (ins i64mem:$src1, i64i8imm:$src2), 1083 "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB; 1084 } // Defs = [EFLAGS] 1085 1086 1087 //===----------------------------------------------------------------------===// 1088 // Atomic support 1089 // 1090 1091 1092 // Atomic swap. These are just normal xchg instructions. But since a memory 1093 // operand is referenced, the atomicity is ensured. 1094 let Constraints = "$val = $dst" in { 1095 def XCHG8rm : I<0x86, MRMSrcMem, (outs GR8:$dst), (ins GR8:$val, i8mem:$ptr), 1096 "xchg{b}\t{$val, $ptr|$ptr, $val}", 1097 [(set GR8:$dst, (atomic_swap_8 addr:$ptr, GR8:$val))]>; 1098 def XCHG16rm : I<0x87, MRMSrcMem, (outs GR16:$dst),(ins GR16:$val, i16mem:$ptr), 1099 "xchg{w}\t{$val, $ptr|$ptr, $val}", 1100 [(set GR16:$dst, (atomic_swap_16 addr:$ptr, GR16:$val))]>, 1101 OpSize; 1102 def XCHG32rm : I<0x87, MRMSrcMem, (outs GR32:$dst),(ins GR32:$val, i32mem:$ptr), 1103 "xchg{l}\t{$val, $ptr|$ptr, $val}", 1104 [(set GR32:$dst, (atomic_swap_32 addr:$ptr, GR32:$val))]>; 1105 def XCHG64rm : RI<0x87, MRMSrcMem, (outs GR64:$dst),(ins GR64:$val,i64mem:$ptr), 1106 "xchg{q}\t{$val, $ptr|$ptr, $val}", 1107 [(set GR64:$dst, (atomic_swap_64 addr:$ptr, GR64:$val))]>; 1108 1109 def XCHG8rr : I<0x86, MRMSrcReg, (outs GR8:$dst), (ins GR8:$val, GR8:$src), 1110 "xchg{b}\t{$val, $src|$src, $val}", []>; 1111 def XCHG16rr : I<0x87, MRMSrcReg, (outs GR16:$dst), (ins GR16:$val, GR16:$src), 1112 "xchg{w}\t{$val, $src|$src, $val}", []>, OpSize; 1113 def XCHG32rr : I<0x87, MRMSrcReg, (outs GR32:$dst), (ins GR32:$val, GR32:$src), 1114 "xchg{l}\t{$val, $src|$src, $val}", []>; 1115 def XCHG64rr : RI<0x87, MRMSrcReg, (outs GR64:$dst), (ins GR64:$val,GR64:$src), 1116 "xchg{q}\t{$val, $src|$src, $val}", []>; 1117 } 1118 1119 def XCHG16ar : I<0x90, AddRegFrm, (outs), (ins GR16:$src), 1120 "xchg{w}\t{$src, %ax|%ax, $src}", []>, OpSize; 1121 def XCHG32ar : I<0x90, AddRegFrm, (outs), (ins GR32:$src), 1122 "xchg{l}\t{$src, %eax|%eax, $src}", []>; 1123 def XCHG64ar : RI<0x90, AddRegFrm, (outs), (ins GR64:$src), 1124 "xchg{q}\t{$src, %rax|%rax, $src}", []>; 1125 1126 1127 1128 def XADD8rr : I<0xC0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src), 1129 "xadd{b}\t{$src, $dst|$dst, $src}", []>, TB; 1130 def XADD16rr : I<0xC1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src), 1131 "xadd{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize; 1132 def XADD32rr : I<0xC1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src), 1133 "xadd{l}\t{$src, $dst|$dst, $src}", []>, TB; 1134 def XADD64rr : RI<0xC1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src), 1135 "xadd{q}\t{$src, $dst|$dst, $src}", []>, TB; 1136 1137 let mayLoad = 1, mayStore = 1 in { 1138 def XADD8rm : I<0xC0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src), 1139 "xadd{b}\t{$src, $dst|$dst, $src}", []>, TB; 1140 def XADD16rm : I<0xC1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src), 1141 "xadd{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize; 1142 def XADD32rm : I<0xC1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), 1143 "xadd{l}\t{$src, $dst|$dst, $src}", []>, TB; 1144 def XADD64rm : RI<0xC1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src), 1145 "xadd{q}\t{$src, $dst|$dst, $src}", []>, TB; 1146 1147 } 1148 1149 def CMPXCHG8rr : I<0xB0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src), 1150 "cmpxchg{b}\t{$src, $dst|$dst, $src}", []>, TB; 1151 def CMPXCHG16rr : I<0xB1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src), 1152 "cmpxchg{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize; 1153 def CMPXCHG32rr : I<0xB1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src), 1154 "cmpxchg{l}\t{$src, $dst|$dst, $src}", []>, TB; 1155 def CMPXCHG64rr : RI<0xB1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src), 1156 "cmpxchg{q}\t{$src, $dst|$dst, $src}", []>, TB; 1157 1158 let mayLoad = 1, mayStore = 1 in { 1159 def CMPXCHG8rm : I<0xB0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src), 1160 "cmpxchg{b}\t{$src, $dst|$dst, $src}", []>, TB; 1161 def CMPXCHG16rm : I<0xB1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src), 1162 "cmpxchg{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize; 1163 def CMPXCHG32rm : I<0xB1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), 1164 "cmpxchg{l}\t{$src, $dst|$dst, $src}", []>, TB; 1165 def CMPXCHG64rm : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src), 1166 "cmpxchg{q}\t{$src, $dst|$dst, $src}", []>, TB; 1167 } 1168 1169 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in 1170 def CMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$dst), 1171 "cmpxchg8b\t$dst", []>, TB; 1172 1173 let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX] in 1174 def CMPXCHG16B : RI<0xC7, MRM1m, (outs), (ins i128mem:$dst), 1175 "cmpxchg16b\t$dst", []>, TB; 1176 1177 1178 1179 // Lock instruction prefix 1180 def LOCK_PREFIX : I<0xF0, RawFrm, (outs), (ins), "lock", []>; 1181 1182 // Rex64 instruction prefix 1183 def REX64_PREFIX : I<0x48, RawFrm, (outs), (ins), "rex64", []>; 1184 1185 // Data16 instruction prefix 1186 def DATA16_PREFIX : I<0x66, RawFrm, (outs), (ins), "data16", []>; 1187 1188 // Repeat string operation instruction prefixes 1189 // These uses the DF flag in the EFLAGS register to inc or dec ECX 1190 let Defs = [ECX], Uses = [ECX,EFLAGS] in { 1191 // Repeat (used with INS, OUTS, MOVS, LODS and STOS) 1192 def REP_PREFIX : I<0xF3, RawFrm, (outs), (ins), "rep", []>; 1193 // Repeat while not equal (used with CMPS and SCAS) 1194 def REPNE_PREFIX : I<0xF2, RawFrm, (outs), (ins), "repne", []>; 1195 } 1196 1197 1198 // String manipulation instructions 1199 def LODSB : I<0xAC, RawFrm, (outs), (ins), "lodsb", []>; 1200 def LODSW : I<0xAD, RawFrm, (outs), (ins), "lodsw", []>, OpSize; 1201 def LODSD : I<0xAD, RawFrm, (outs), (ins), "lods{l|d}", []>; 1202 def LODSQ : RI<0xAD, RawFrm, (outs), (ins), "lodsq", []>; 1203 1204 def OUTSB : I<0x6E, RawFrm, (outs), (ins), "outsb", []>; 1205 def OUTSW : I<0x6F, RawFrm, (outs), (ins), "outsw", []>, OpSize; 1206 def OUTSD : I<0x6F, RawFrm, (outs), (ins), "outs{l|d}", []>; 1207 1208 1209 // Flag instructions 1210 def CLC : I<0xF8, RawFrm, (outs), (ins), "clc", []>; 1211 def STC : I<0xF9, RawFrm, (outs), (ins), "stc", []>; 1212 def CLI : I<0xFA, RawFrm, (outs), (ins), "cli", []>; 1213 def STI : I<0xFB, RawFrm, (outs), (ins), "sti", []>; 1214 def CLD : I<0xFC, RawFrm, (outs), (ins), "cld", []>; 1215 def STD : I<0xFD, RawFrm, (outs), (ins), "std", []>; 1216 def CMC : I<0xF5, RawFrm, (outs), (ins), "cmc", []>; 1217 1218 def CLTS : I<0x06, RawFrm, (outs), (ins), "clts", []>, TB; 1219 1220 // Table lookup instructions 1221 def XLAT : I<0xD7, RawFrm, (outs), (ins), "xlatb", []>; 1222 1223 // ASCII Adjust After Addition 1224 // sets AL, AH and CF and AF of EFLAGS and uses AL and AF of EFLAGS 1225 def AAA : I<0x37, RawFrm, (outs), (ins), "aaa", []>, Requires<[In32BitMode]>; 1226 1227 // ASCII Adjust AX Before Division 1228 // sets AL, AH and EFLAGS and uses AL and AH 1229 def AAD8i8 : Ii8<0xD5, RawFrm, (outs), (ins i8imm:$src), 1230 "aad\t$src", []>, Requires<[In32BitMode]>; 1231 1232 // ASCII Adjust AX After Multiply 1233 // sets AL, AH and EFLAGS and uses AL 1234 def AAM8i8 : Ii8<0xD4, RawFrm, (outs), (ins i8imm:$src), 1235 "aam\t$src", []>, Requires<[In32BitMode]>; 1236 1237 // ASCII Adjust AL After Subtraction - sets 1238 // sets AL, AH and CF and AF of EFLAGS and uses AL and AF of EFLAGS 1239 def AAS : I<0x3F, RawFrm, (outs), (ins), "aas", []>, Requires<[In32BitMode]>; 1240 1241 // Decimal Adjust AL after Addition 1242 // sets AL, CF and AF of EFLAGS and uses AL, CF and AF of EFLAGS 1243 def DAA : I<0x27, RawFrm, (outs), (ins), "daa", []>, Requires<[In32BitMode]>; 1244 1245 // Decimal Adjust AL after Subtraction 1246 // sets AL, CF and AF of EFLAGS and uses AL, CF and AF of EFLAGS 1247 def DAS : I<0x2F, RawFrm, (outs), (ins), "das", []>, Requires<[In32BitMode]>; 1248 1249 // Check Array Index Against Bounds 1250 def BOUNDS16rm : I<0x62, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), 1251 "bound\t{$src, $dst|$dst, $src}", []>, OpSize, 1252 Requires<[In32BitMode]>; 1253 def BOUNDS32rm : I<0x62, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), 1254 "bound\t{$src, $dst|$dst, $src}", []>, 1255 Requires<[In32BitMode]>; 1256 1257 // Adjust RPL Field of Segment Selector 1258 def ARPL16rr : I<0x63, MRMDestReg, (outs GR16:$src), (ins GR16:$dst), 1259 "arpl\t{$src, $dst|$dst, $src}", []>, Requires<[In32BitMode]>; 1260 def ARPL16mr : I<0x63, MRMSrcMem, (outs GR16:$src), (ins i16mem:$dst), 1261 "arpl\t{$src, $dst|$dst, $src}", []>, Requires<[In32BitMode]>; 1262 1263 //===----------------------------------------------------------------------===// 1264 // Subsystems. 1265 //===----------------------------------------------------------------------===// 1266 1267 include "X86InstrArithmetic.td" 1268 include "X86InstrCMovSetCC.td" 1269 include "X86InstrExtension.td" 1270 include "X86InstrControl.td" 1271 include "X86InstrShiftRotate.td" 1272 1273 // X87 Floating Point Stack. 1274 include "X86InstrFPStack.td" 1275 1276 // SIMD support (SSE, MMX and AVX) 1277 include "X86InstrFragmentsSIMD.td" 1278 1279 // FMA - Fused Multiply-Add support (requires FMA) 1280 include "X86InstrFMA.td" 1281 1282 // SSE, MMX and 3DNow! vector support. 1283 include "X86InstrSSE.td" 1284 include "X86InstrMMX.td" 1285 include "X86Instr3DNow.td" 1286 1287 include "X86InstrVMX.td" 1288 1289 // System instructions. 1290 include "X86InstrSystem.td" 1291 1292 // Compiler Pseudo Instructions and Pat Patterns 1293 include "X86InstrCompiler.td" 1294 1295 //===----------------------------------------------------------------------===// 1296 // Assembler Mnemonic Aliases 1297 //===----------------------------------------------------------------------===// 1298 1299 def : MnemonicAlias<"call", "calll">, Requires<[In32BitMode]>; 1300 def : MnemonicAlias<"call", "callq">, Requires<[In64BitMode]>; 1301 1302 def : MnemonicAlias<"cbw", "cbtw">; 1303 def : MnemonicAlias<"cwd", "cwtd">; 1304 def : MnemonicAlias<"cdq", "cltd">; 1305 def : MnemonicAlias<"cwde", "cwtl">; 1306 def : MnemonicAlias<"cdqe", "cltq">; 1307 1308 // lret maps to lretl, it is not ambiguous with lretq. 1309 def : MnemonicAlias<"lret", "lretl">; 1310 1311 def : MnemonicAlias<"leavel", "leave">, Requires<[In32BitMode]>; 1312 def : MnemonicAlias<"leaveq", "leave">, Requires<[In64BitMode]>; 1313 1314 def : MnemonicAlias<"loopz", "loope">; 1315 def : MnemonicAlias<"loopnz", "loopne">; 1316 1317 def : MnemonicAlias<"pop", "popl">, Requires<[In32BitMode]>; 1318 def : MnemonicAlias<"pop", "popq">, Requires<[In64BitMode]>; 1319 def : MnemonicAlias<"popf", "popfl">, Requires<[In32BitMode]>; 1320 def : MnemonicAlias<"popf", "popfq">, Requires<[In64BitMode]>; 1321 def : MnemonicAlias<"popfd", "popfl">; 1322 1323 // FIXME: This is wrong for "push reg". "push %bx" should turn into pushw in 1324 // all modes. However: "push (addr)" and "push $42" should default to 1325 // pushl/pushq depending on the current mode. Similar for "pop %bx" 1326 def : MnemonicAlias<"push", "pushl">, Requires<[In32BitMode]>; 1327 def : MnemonicAlias<"push", "pushq">, Requires<[In64BitMode]>; 1328 def : MnemonicAlias<"pushf", "pushfl">, Requires<[In32BitMode]>; 1329 def : MnemonicAlias<"pushf", "pushfq">, Requires<[In64BitMode]>; 1330 def : MnemonicAlias<"pushfd", "pushfl">; 1331 1332 def : MnemonicAlias<"repe", "rep">; 1333 def : MnemonicAlias<"repz", "rep">; 1334 def : MnemonicAlias<"repnz", "repne">; 1335 1336 def : MnemonicAlias<"retl", "ret">, Requires<[In32BitMode]>; 1337 def : MnemonicAlias<"retq", "ret">, Requires<[In64BitMode]>; 1338 1339 def : MnemonicAlias<"salb", "shlb">; 1340 def : MnemonicAlias<"salw", "shlw">; 1341 def : MnemonicAlias<"sall", "shll">; 1342 def : MnemonicAlias<"salq", "shlq">; 1343 1344 def : MnemonicAlias<"smovb", "movsb">; 1345 def : MnemonicAlias<"smovw", "movsw">; 1346 def : MnemonicAlias<"smovl", "movsl">; 1347 def : MnemonicAlias<"smovq", "movsq">; 1348 1349 def : MnemonicAlias<"ud2a", "ud2">; 1350 def : MnemonicAlias<"verrw", "verr">; 1351 1352 // System instruction aliases. 1353 def : MnemonicAlias<"iret", "iretl">; 1354 def : MnemonicAlias<"sysret", "sysretl">; 1355 1356 def : MnemonicAlias<"lgdtl", "lgdt">, Requires<[In32BitMode]>; 1357 def : MnemonicAlias<"lgdtq", "lgdt">, Requires<[In64BitMode]>; 1358 def : MnemonicAlias<"lidtl", "lidt">, Requires<[In32BitMode]>; 1359 def : MnemonicAlias<"lidtq", "lidt">, Requires<[In64BitMode]>; 1360 def : MnemonicAlias<"sgdtl", "sgdt">, Requires<[In32BitMode]>; 1361 def : MnemonicAlias<"sgdtq", "sgdt">, Requires<[In64BitMode]>; 1362 def : MnemonicAlias<"sidtl", "sidt">, Requires<[In32BitMode]>; 1363 def : MnemonicAlias<"sidtq", "sidt">, Requires<[In64BitMode]>; 1364 1365 1366 // Floating point stack aliases. 1367 def : MnemonicAlias<"fcmovz", "fcmove">; 1368 def : MnemonicAlias<"fcmova", "fcmovnbe">; 1369 def : MnemonicAlias<"fcmovnae", "fcmovb">; 1370 def : MnemonicAlias<"fcmovna", "fcmovbe">; 1371 def : MnemonicAlias<"fcmovae", "fcmovnb">; 1372 def : MnemonicAlias<"fcomip", "fcompi">; 1373 def : MnemonicAlias<"fildq", "fildll">; 1374 def : MnemonicAlias<"fldcww", "fldcw">; 1375 def : MnemonicAlias<"fnstcww", "fnstcw">; 1376 def : MnemonicAlias<"fnstsww", "fnstsw">; 1377 def : MnemonicAlias<"fucomip", "fucompi">; 1378 def : MnemonicAlias<"fwait", "wait">; 1379 1380 1381 class CondCodeAlias<string Prefix,string Suffix, string OldCond, string NewCond> 1382 : MnemonicAlias<!strconcat(Prefix, OldCond, Suffix), 1383 !strconcat(Prefix, NewCond, Suffix)>; 1384 1385 /// IntegerCondCodeMnemonicAlias - This multiclass defines a bunch of 1386 /// MnemonicAlias's that canonicalize the condition code in a mnemonic, for 1387 /// example "setz" -> "sete". 1388 multiclass IntegerCondCodeMnemonicAlias<string Prefix, string Suffix> { 1389 def C : CondCodeAlias<Prefix, Suffix, "c", "b">; // setc -> setb 1390 def Z : CondCodeAlias<Prefix, Suffix, "z" , "e">; // setz -> sete 1391 def NA : CondCodeAlias<Prefix, Suffix, "na", "be">; // setna -> setbe 1392 def NB : CondCodeAlias<Prefix, Suffix, "nb", "ae">; // setnb -> setae 1393 def NC : CondCodeAlias<Prefix, Suffix, "nc", "ae">; // setnc -> setae 1394 def NG : CondCodeAlias<Prefix, Suffix, "ng", "le">; // setng -> setle 1395 def NL : CondCodeAlias<Prefix, Suffix, "nl", "ge">; // setnl -> setge 1396 def NZ : CondCodeAlias<Prefix, Suffix, "nz", "ne">; // setnz -> setne 1397 def PE : CondCodeAlias<Prefix, Suffix, "pe", "p">; // setpe -> setp 1398 def PO : CondCodeAlias<Prefix, Suffix, "po", "np">; // setpo -> setnp 1399 1400 def NAE : CondCodeAlias<Prefix, Suffix, "nae", "b">; // setnae -> setb 1401 def NBE : CondCodeAlias<Prefix, Suffix, "nbe", "a">; // setnbe -> seta 1402 def NGE : CondCodeAlias<Prefix, Suffix, "nge", "l">; // setnge -> setl 1403 def NLE : CondCodeAlias<Prefix, Suffix, "nle", "g">; // setnle -> setg 1404 } 1405 1406 // Aliases for set<CC> 1407 defm : IntegerCondCodeMnemonicAlias<"set", "">; 1408 // Aliases for j<CC> 1409 defm : IntegerCondCodeMnemonicAlias<"j", "">; 1410 // Aliases for cmov<CC>{w,l,q} 1411 defm : IntegerCondCodeMnemonicAlias<"cmov", "w">; 1412 defm : IntegerCondCodeMnemonicAlias<"cmov", "l">; 1413 defm : IntegerCondCodeMnemonicAlias<"cmov", "q">; 1414 1415 1416 //===----------------------------------------------------------------------===// 1417 // Assembler Instruction Aliases 1418 //===----------------------------------------------------------------------===// 1419 1420 // aad/aam default to base 10 if no operand is specified. 1421 def : InstAlias<"aad", (AAD8i8 10)>; 1422 def : InstAlias<"aam", (AAM8i8 10)>; 1423 1424 // Disambiguate the mem/imm form of bt-without-a-suffix as btl. 1425 def : InstAlias<"bt $imm, $mem", (BT32mi8 i32mem:$mem, i32i8imm:$imm)>; 1426 1427 // clr aliases. 1428 def : InstAlias<"clrb $reg", (XOR8rr GR8 :$reg, GR8 :$reg)>; 1429 def : InstAlias<"clrw $reg", (XOR16rr GR16:$reg, GR16:$reg)>; 1430 def : InstAlias<"clrl $reg", (XOR32rr GR32:$reg, GR32:$reg)>; 1431 def : InstAlias<"clrq $reg", (XOR64rr GR64:$reg, GR64:$reg)>; 1432 1433 // div and idiv aliases for explicit A register. 1434 def : InstAlias<"divb $src, %al", (DIV8r GR8 :$src)>; 1435 def : InstAlias<"divw $src, %ax", (DIV16r GR16:$src)>; 1436 def : InstAlias<"divl $src, %eax", (DIV32r GR32:$src)>; 1437 def : InstAlias<"divq $src, %rax", (DIV64r GR64:$src)>; 1438 def : InstAlias<"divb $src, %al", (DIV8m i8mem :$src)>; 1439 def : InstAlias<"divw $src, %ax", (DIV16m i16mem:$src)>; 1440 def : InstAlias<"divl $src, %eax", (DIV32m i32mem:$src)>; 1441 def : InstAlias<"divq $src, %rax", (DIV64m i64mem:$src)>; 1442 def : InstAlias<"idivb $src, %al", (IDIV8r GR8 :$src)>; 1443 def : InstAlias<"idivw $src, %ax", (IDIV16r GR16:$src)>; 1444 def : InstAlias<"idivl $src, %eax", (IDIV32r GR32:$src)>; 1445 def : InstAlias<"idivq $src, %rax", (IDIV64r GR64:$src)>; 1446 def : InstAlias<"idivb $src, %al", (IDIV8m i8mem :$src)>; 1447 def : InstAlias<"idivw $src, %ax", (IDIV16m i16mem:$src)>; 1448 def : InstAlias<"idivl $src, %eax", (IDIV32m i32mem:$src)>; 1449 def : InstAlias<"idivq $src, %rax", (IDIV64m i64mem:$src)>; 1450 1451 1452 1453 // Various unary fpstack operations default to operating on on ST1. 1454 // For example, "fxch" -> "fxch %st(1)" 1455 def : InstAlias<"faddp", (ADD_FPrST0 ST1), 0>; 1456 def : InstAlias<"fsubp", (SUBR_FPrST0 ST1)>; 1457 def : InstAlias<"fsubrp", (SUB_FPrST0 ST1)>; 1458 def : InstAlias<"fmulp", (MUL_FPrST0 ST1)>; 1459 def : InstAlias<"fdivp", (DIVR_FPrST0 ST1)>; 1460 def : InstAlias<"fdivrp", (DIV_FPrST0 ST1)>; 1461 def : InstAlias<"fxch", (XCH_F ST1)>; 1462 def : InstAlias<"fcomi", (COM_FIr ST1)>; 1463 def : InstAlias<"fcompi", (COM_FIPr ST1)>; 1464 def : InstAlias<"fucom", (UCOM_Fr ST1)>; 1465 def : InstAlias<"fucomp", (UCOM_FPr ST1)>; 1466 def : InstAlias<"fucomi", (UCOM_FIr ST1)>; 1467 def : InstAlias<"fucompi", (UCOM_FIPr ST1)>; 1468 1469 // Handle fmul/fadd/fsub/fdiv instructions with explicitly written st(0) op. 1470 // For example, "fadd %st(4), %st(0)" -> "fadd %st(4)". We also disambiguate 1471 // instructions like "fadd %st(0), %st(0)" as "fadd %st(0)" for consistency with 1472 // gas. 1473 multiclass FpUnaryAlias<string Mnemonic, Instruction Inst, bit EmitAlias = 1> { 1474 def : InstAlias<!strconcat(Mnemonic, " $op, %st(0)"), 1475 (Inst RST:$op), EmitAlias>; 1476 def : InstAlias<!strconcat(Mnemonic, " %st(0), %st(0)"), 1477 (Inst ST0), EmitAlias>; 1478 } 1479 1480 defm : FpUnaryAlias<"fadd", ADD_FST0r>; 1481 defm : FpUnaryAlias<"faddp", ADD_FPrST0, 0>; 1482 defm : FpUnaryAlias<"fsub", SUB_FST0r>; 1483 defm : FpUnaryAlias<"fsubp", SUBR_FPrST0>; 1484 defm : FpUnaryAlias<"fsubr", SUBR_FST0r>; 1485 defm : FpUnaryAlias<"fsubrp", SUB_FPrST0>; 1486 defm : FpUnaryAlias<"fmul", MUL_FST0r>; 1487 defm : FpUnaryAlias<"fmulp", MUL_FPrST0>; 1488 defm : FpUnaryAlias<"fdiv", DIV_FST0r>; 1489 defm : FpUnaryAlias<"fdivp", DIVR_FPrST0>; 1490 defm : FpUnaryAlias<"fdivr", DIVR_FST0r>; 1491 defm : FpUnaryAlias<"fdivrp", DIV_FPrST0>; 1492 defm : FpUnaryAlias<"fcomi", COM_FIr, 0>; 1493 defm : FpUnaryAlias<"fucomi", UCOM_FIr, 0>; 1494 defm : FpUnaryAlias<"fcompi", COM_FIPr>; 1495 defm : FpUnaryAlias<"fucompi", UCOM_FIPr>; 1496 1497 1498 // Handle "f{mulp,addp} st(0), $op" the same as "f{mulp,addp} $op", since they 1499 // commute. We also allow fdiv[r]p/fsubrp even though they don't commute, 1500 // solely because gas supports it. 1501 def : InstAlias<"faddp %st(0), $op", (ADD_FPrST0 RST:$op), 0>; 1502 def : InstAlias<"fmulp %st(0), $op", (MUL_FPrST0 RST:$op)>; 1503 def : InstAlias<"fsubp %st(0), $op", (SUBR_FPrST0 RST:$op)>; 1504 def : InstAlias<"fsubrp %st(0), $op", (SUB_FPrST0 RST:$op)>; 1505 def : InstAlias<"fdivp %st(0), $op", (DIVR_FPrST0 RST:$op)>; 1506 def : InstAlias<"fdivrp %st(0), $op", (DIV_FPrST0 RST:$op)>; 1507 1508 // We accept "fnstsw %eax" even though it only writes %ax. 1509 def : InstAlias<"fnstsw %eax", (FNSTSW8r)>; 1510 def : InstAlias<"fnstsw %al" , (FNSTSW8r)>; 1511 def : InstAlias<"fnstsw" , (FNSTSW8r)>; 1512 1513 // lcall and ljmp aliases. This seems to be an odd mapping in 64-bit mode, but 1514 // this is compatible with what GAS does. 1515 def : InstAlias<"lcall $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>; 1516 def : InstAlias<"ljmp $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>; 1517 def : InstAlias<"lcall *$dst", (FARCALL32m opaque48mem:$dst)>; 1518 def : InstAlias<"ljmp *$dst", (FARJMP32m opaque48mem:$dst)>; 1519 1520 // "imul <imm>, B" is an alias for "imul <imm>, B, B". 1521 def : InstAlias<"imulw $imm, $r", (IMUL16rri GR16:$r, GR16:$r, i16imm:$imm)>; 1522 def : InstAlias<"imulw $imm, $r", (IMUL16rri8 GR16:$r, GR16:$r, i16i8imm:$imm)>; 1523 def : InstAlias<"imull $imm, $r", (IMUL32rri GR32:$r, GR32:$r, i32imm:$imm)>; 1524 def : InstAlias<"imull $imm, $r", (IMUL32rri8 GR32:$r, GR32:$r, i32i8imm:$imm)>; 1525 def : InstAlias<"imulq $imm, $r",(IMUL64rri32 GR64:$r, GR64:$r,i64i32imm:$imm)>; 1526 def : InstAlias<"imulq $imm, $r", (IMUL64rri8 GR64:$r, GR64:$r, i64i8imm:$imm)>; 1527 1528 // inb %dx -> inb %al, %dx 1529 def : InstAlias<"inb %dx", (IN8rr)>; 1530 def : InstAlias<"inw %dx", (IN16rr)>; 1531 def : InstAlias<"inl %dx", (IN32rr)>; 1532 def : InstAlias<"inb $port", (IN8ri i8imm:$port)>; 1533 def : InstAlias<"inw $port", (IN16ri i8imm:$port)>; 1534 def : InstAlias<"inl $port", (IN32ri i8imm:$port)>; 1535 1536 1537 // jmp and call aliases for lcall and ljmp. jmp $42,$5 -> ljmp 1538 def : InstAlias<"call $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>; 1539 def : InstAlias<"jmp $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>; 1540 def : InstAlias<"callw $seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg)>; 1541 def : InstAlias<"jmpw $seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg)>; 1542 def : InstAlias<"calll $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>; 1543 def : InstAlias<"jmpl $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>; 1544 1545 // Force mov without a suffix with a segment and mem to prefer the 'l' form of 1546 // the move. All segment/mem forms are equivalent, this has the shortest 1547 // encoding. 1548 def : InstAlias<"mov $mem, $seg", (MOV32sm SEGMENT_REG:$seg, i32mem:$mem)>; 1549 def : InstAlias<"mov $seg, $mem", (MOV32ms i32mem:$mem, SEGMENT_REG:$seg)>; 1550 1551 // Match 'movq <largeimm>, <reg>' as an alias for movabsq. 1552 def : InstAlias<"movq $imm, $reg", (MOV64ri GR64:$reg, i64imm:$imm)>; 1553 1554 // Match 'movq GR64, MMX' as an alias for movd. 1555 def : InstAlias<"movq $src, $dst", 1556 (MMX_MOVD64to64rr VR64:$dst, GR64:$src), 0>; 1557 def : InstAlias<"movq $src, $dst", 1558 (MMX_MOVD64from64rr GR64:$dst, VR64:$src), 0>; 1559 1560 // movsd with no operands (as opposed to the SSE scalar move of a double) is an 1561 // alias for movsl. (as in rep; movsd) 1562 def : InstAlias<"movsd", (MOVSD)>; 1563 1564 // movsx aliases 1565 def : InstAlias<"movsx $src, $dst", (MOVSX16rr8 GR16:$dst, GR8:$src), 0>; 1566 def : InstAlias<"movsx $src, $dst", (MOVSX16rm8 GR16:$dst, i8mem:$src), 0>; 1567 def : InstAlias<"movsx $src, $dst", (MOVSX32rr8 GR32:$dst, GR8:$src), 0>; 1568 def : InstAlias<"movsx $src, $dst", (MOVSX32rr16 GR32:$dst, GR16:$src), 0>; 1569 def : InstAlias<"movsx $src, $dst", (MOVSX64rr8 GR64:$dst, GR8:$src), 0>; 1570 def : InstAlias<"movsx $src, $dst", (MOVSX64rr16 GR64:$dst, GR16:$src), 0>; 1571 def : InstAlias<"movsx $src, $dst", (MOVSX64rr32 GR64:$dst, GR32:$src), 0>; 1572 1573 // movzx aliases 1574 def : InstAlias<"movzx $src, $dst", (MOVZX16rr8 GR16:$dst, GR8:$src), 0>; 1575 def : InstAlias<"movzx $src, $dst", (MOVZX16rm8 GR16:$dst, i8mem:$src), 0>; 1576 def : InstAlias<"movzx $src, $dst", (MOVZX32rr8 GR32:$dst, GR8:$src), 0>; 1577 def : InstAlias<"movzx $src, $dst", (MOVZX32rr16 GR32:$dst, GR16:$src), 0>; 1578 def : InstAlias<"movzx $src, $dst", (MOVZX64rr8_Q GR64:$dst, GR8:$src), 0>; 1579 def : InstAlias<"movzx $src, $dst", (MOVZX64rr16_Q GR64:$dst, GR16:$src), 0>; 1580 // Note: No GR32->GR64 movzx form. 1581 1582 // outb %dx -> outb %al, %dx 1583 def : InstAlias<"outb %dx", (OUT8rr)>; 1584 def : InstAlias<"outw %dx", (OUT16rr)>; 1585 def : InstAlias<"outl %dx", (OUT32rr)>; 1586 def : InstAlias<"outb $port", (OUT8ir i8imm:$port)>; 1587 def : InstAlias<"outw $port", (OUT16ir i8imm:$port)>; 1588 def : InstAlias<"outl $port", (OUT32ir i8imm:$port)>; 1589 1590 // 'sldt <mem>' can be encoded with either sldtw or sldtq with the same 1591 // effect (both store to a 16-bit mem). Force to sldtw to avoid ambiguity 1592 // errors, since its encoding is the most compact. 1593 def : InstAlias<"sldt $mem", (SLDT16m i16mem:$mem)>; 1594 1595 // shld/shrd op,op -> shld op, op, 1 1596 def : InstAlias<"shldw $r1, $r2", (SHLD16rri8 GR16:$r1, GR16:$r2, 1)>; 1597 def : InstAlias<"shldl $r1, $r2", (SHLD32rri8 GR32:$r1, GR32:$r2, 1)>; 1598 def : InstAlias<"shldq $r1, $r2", (SHLD64rri8 GR64:$r1, GR64:$r2, 1)>; 1599 def : InstAlias<"shrdw $r1, $r2", (SHRD16rri8 GR16:$r1, GR16:$r2, 1)>; 1600 def : InstAlias<"shrdl $r1, $r2", (SHRD32rri8 GR32:$r1, GR32:$r2, 1)>; 1601 def : InstAlias<"shrdq $r1, $r2", (SHRD64rri8 GR64:$r1, GR64:$r2, 1)>; 1602 1603 def : InstAlias<"shldw $mem, $reg", (SHLD16mri8 i16mem:$mem, GR16:$reg, 1)>; 1604 def : InstAlias<"shldl $mem, $reg", (SHLD32mri8 i32mem:$mem, GR32:$reg, 1)>; 1605 def : InstAlias<"shldq $mem, $reg", (SHLD64mri8 i64mem:$mem, GR64:$reg, 1)>; 1606 def : InstAlias<"shrdw $mem, $reg", (SHRD16mri8 i16mem:$mem, GR16:$reg, 1)>; 1607 def : InstAlias<"shrdl $mem, $reg", (SHRD32mri8 i32mem:$mem, GR32:$reg, 1)>; 1608 def : InstAlias<"shrdq $mem, $reg", (SHRD64mri8 i64mem:$mem, GR64:$reg, 1)>; 1609 1610 /* FIXME: This is disabled because the asm matcher is currently incapable of 1611 * matching a fixed immediate like $1. 1612 // "shl X, $1" is an alias for "shl X". 1613 multiclass ShiftRotateByOneAlias<string Mnemonic, string Opc> { 1614 def : InstAlias<!strconcat(Mnemonic, "b $op, $$1"), 1615 (!cast<Instruction>(!strconcat(Opc, "8r1")) GR8:$op)>; 1616 def : InstAlias<!strconcat(Mnemonic, "w $op, $$1"), 1617 (!cast<Instruction>(!strconcat(Opc, "16r1")) GR16:$op)>; 1618 def : InstAlias<!strconcat(Mnemonic, "l $op, $$1"), 1619 (!cast<Instruction>(!strconcat(Opc, "32r1")) GR32:$op)>; 1620 def : InstAlias<!strconcat(Mnemonic, "q $op, $$1"), 1621 (!cast<Instruction>(!strconcat(Opc, "64r1")) GR64:$op)>; 1622 def : InstAlias<!strconcat(Mnemonic, "b $op, $$1"), 1623 (!cast<Instruction>(!strconcat(Opc, "8m1")) i8mem:$op)>; 1624 def : InstAlias<!strconcat(Mnemonic, "w $op, $$1"), 1625 (!cast<Instruction>(!strconcat(Opc, "16m1")) i16mem:$op)>; 1626 def : InstAlias<!strconcat(Mnemonic, "l $op, $$1"), 1627 (!cast<Instruction>(!strconcat(Opc, "32m1")) i32mem:$op)>; 1628 def : InstAlias<!strconcat(Mnemonic, "q $op, $$1"), 1629 (!cast<Instruction>(!strconcat(Opc, "64m1")) i64mem:$op)>; 1630 } 1631 1632 defm : ShiftRotateByOneAlias<"rcl", "RCL">; 1633 defm : ShiftRotateByOneAlias<"rcr", "RCR">; 1634 defm : ShiftRotateByOneAlias<"rol", "ROL">; 1635 defm : ShiftRotateByOneAlias<"ror", "ROR">; 1636 FIXME */ 1637 1638 // test: We accept "testX <reg>, <mem>" and "testX <mem>, <reg>" as synonyms. 1639 def : InstAlias<"testb $val, $mem", (TEST8rm GR8 :$val, i8mem :$mem)>; 1640 def : InstAlias<"testw $val, $mem", (TEST16rm GR16:$val, i16mem:$mem)>; 1641 def : InstAlias<"testl $val, $mem", (TEST32rm GR32:$val, i32mem:$mem)>; 1642 def : InstAlias<"testq $val, $mem", (TEST64rm GR64:$val, i64mem:$mem)>; 1643 1644 // xchg: We accept "xchgX <reg>, <mem>" and "xchgX <mem>, <reg>" as synonyms. 1645 def : InstAlias<"xchgb $mem, $val", (XCHG8rm GR8 :$val, i8mem :$mem)>; 1646 def : InstAlias<"xchgw $mem, $val", (XCHG16rm GR16:$val, i16mem:$mem)>; 1647 def : InstAlias<"xchgl $mem, $val", (XCHG32rm GR32:$val, i32mem:$mem)>; 1648 def : InstAlias<"xchgq $mem, $val", (XCHG64rm GR64:$val, i64mem:$mem)>; 1649
