1 //====- X86InstrMMX.td - Describe the MMX Instruction Set --*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file describes the X86 MMX instruction set, defining the instructions, 11 // and properties of the instructions which are needed for code generation, 12 // machine code emission, and analysis. 13 // 14 // All instructions that use MMX should be in this file, even if they also use 15 // SSE. 16 // 17 //===----------------------------------------------------------------------===// 18 19 //===----------------------------------------------------------------------===// 20 // MMX Multiclasses 21 //===----------------------------------------------------------------------===// 22 23 let Constraints = "$src1 = $dst" in { 24 // MMXI_binop_rm_int - Simple MMX binary operator based on intrinsic. 25 // When this is cleaned up, remove the FIXME from X86RecognizableInstr.cpp. 26 multiclass MMXI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId, 27 bit Commutable = 0> { 28 def irr : MMXI<opc, MRMSrcReg, (outs VR64:$dst), 29 (ins VR64:$src1, VR64:$src2), 30 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"), 31 [(set VR64:$dst, (IntId VR64:$src1, VR64:$src2))]> { 32 let isCommutable = Commutable; 33 } 34 def irm : MMXI<opc, MRMSrcMem, (outs VR64:$dst), 35 (ins VR64:$src1, i64mem:$src2), 36 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"), 37 [(set VR64:$dst, (IntId VR64:$src1, 38 (bitconvert (load_mmx addr:$src2))))]>; 39 } 40 41 multiclass MMXI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm, 42 string OpcodeStr, Intrinsic IntId, 43 Intrinsic IntId2> { 44 def rr : MMXI<opc, MRMSrcReg, (outs VR64:$dst), 45 (ins VR64:$src1, VR64:$src2), 46 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"), 47 [(set VR64:$dst, (IntId VR64:$src1, VR64:$src2))]>; 48 def rm : MMXI<opc, MRMSrcMem, (outs VR64:$dst), 49 (ins VR64:$src1, i64mem:$src2), 50 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"), 51 [(set VR64:$dst, (IntId VR64:$src1, 52 (bitconvert (load_mmx addr:$src2))))]>; 53 def ri : MMXIi8<opc2, ImmForm, (outs VR64:$dst), 54 (ins VR64:$src1, i32i8imm:$src2), 55 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"), 56 [(set VR64:$dst, (IntId2 VR64:$src1, (i32 imm:$src2)))]>; 57 } 58 } 59 60 /// Unary MMX instructions requiring SSSE3. 61 multiclass SS3I_unop_rm_int_mm<bits<8> opc, string OpcodeStr, 62 Intrinsic IntId64> { 63 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src), 64 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), 65 [(set VR64:$dst, (IntId64 VR64:$src))]>; 66 67 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src), 68 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), 69 [(set VR64:$dst, 70 (IntId64 (bitconvert (memopmmx addr:$src))))]>; 71 } 72 73 /// Binary MMX instructions requiring SSSE3. 74 let ImmT = NoImm, Constraints = "$src1 = $dst" in { 75 multiclass SS3I_binop_rm_int_mm<bits<8> opc, string OpcodeStr, 76 Intrinsic IntId64> { 77 let isCommutable = 0 in 78 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst), 79 (ins VR64:$src1, VR64:$src2), 80 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"), 81 [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]>; 82 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst), 83 (ins VR64:$src1, i64mem:$src2), 84 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"), 85 [(set VR64:$dst, 86 (IntId64 VR64:$src1, 87 (bitconvert (memopmmx addr:$src2))))]>; 88 } 89 } 90 91 /// PALIGN MMX instructions (require SSSE3). 92 multiclass ssse3_palign_mm<string asm, Intrinsic IntId> { 93 def R64irr : SS3AI<0x0F, MRMSrcReg, (outs VR64:$dst), 94 (ins VR64:$src1, VR64:$src2, i8imm:$src3), 95 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"), 96 [(set VR64:$dst, (IntId VR64:$src1, VR64:$src2, (i8 imm:$src3)))]>; 97 def R64irm : SS3AI<0x0F, MRMSrcMem, (outs VR64:$dst), 98 (ins VR64:$src1, i64mem:$src2, i8imm:$src3), 99 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"), 100 [(set VR64:$dst, (IntId VR64:$src1, 101 (bitconvert (load_mmx addr:$src2)), (i8 imm:$src3)))]>; 102 } 103 104 multiclass sse12_cvt_pint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC, 105 Intrinsic Int, X86MemOperand x86memop, PatFrag ld_frag, 106 string asm, Domain d> { 107 def irr : PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm, 108 [(set DstRC:$dst, (Int SrcRC:$src))], d>; 109 def irm : PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm, 110 [(set DstRC:$dst, (Int (ld_frag addr:$src)))], d>; 111 } 112 113 multiclass sse12_cvt_pint_3addr<bits<8> opc, RegisterClass SrcRC, 114 RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop, 115 PatFrag ld_frag, string asm, Domain d> { 116 def irr : PI<opc, MRMSrcReg, (outs DstRC:$dst),(ins DstRC:$src1, SrcRC:$src2), 117 asm, [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))], d>; 118 def irm : PI<opc, MRMSrcMem, (outs DstRC:$dst), 119 (ins DstRC:$src1, x86memop:$src2), asm, 120 [(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))], d>; 121 } 122 123 //===----------------------------------------------------------------------===// 124 // MMX EMMS Instruction 125 //===----------------------------------------------------------------------===// 126 127 def MMX_EMMS : MMXI<0x77, RawFrm, (outs), (ins), "emms", 128 [(int_x86_mmx_emms)]>; 129 130 //===----------------------------------------------------------------------===// 131 // MMX Scalar Instructions 132 //===----------------------------------------------------------------------===// 133 134 // Data Transfer Instructions 135 def MMX_MOVD64rr : MMXI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR32:$src), 136 "movd\t{$src, $dst|$dst, $src}", 137 [(set VR64:$dst, 138 (x86mmx (scalar_to_vector GR32:$src)))]>; 139 let canFoldAsLoad = 1 in 140 def MMX_MOVD64rm : MMXI<0x6E, MRMSrcMem, (outs VR64:$dst), (ins i32mem:$src), 141 "movd\t{$src, $dst|$dst, $src}", 142 [(set VR64:$dst, 143 (x86mmx (scalar_to_vector (loadi32 addr:$src))))]>; 144 let mayStore = 1 in 145 def MMX_MOVD64mr : MMXI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR64:$src), 146 "movd\t{$src, $dst|$dst, $src}", []>; 147 def MMX_MOVD64grr : MMXI<0x7E, MRMDestReg, (outs), (ins GR32:$dst, VR64:$src), 148 "movd\t{$src, $dst|$dst, $src}", []>; 149 150 let neverHasSideEffects = 1 in 151 def MMX_MOVD64to64rr : MMXRI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR64:$src), 152 "movd\t{$src, $dst|$dst, $src}", 153 []>; 154 155 // These are 64 bit moves, but since the OS X assembler doesn't 156 // recognize a register-register movq, we write them as 157 // movd. 158 def MMX_MOVD64from64rr : MMXRI<0x7E, MRMDestReg, 159 (outs GR64:$dst), (ins VR64:$src), 160 "movd\t{$src, $dst|$dst, $src}", 161 [(set GR64:$dst, 162 (bitconvert VR64:$src))]>; 163 def MMX_MOVD64rrv164 : MMXRI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR64:$src), 164 "movd\t{$src, $dst|$dst, $src}", 165 [(set VR64:$dst, 166 (bitconvert GR64:$src))]>; 167 let neverHasSideEffects = 1 in 168 def MMX_MOVQ64rr : MMXI<0x6F, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src), 169 "movq\t{$src, $dst|$dst, $src}", []>; 170 let canFoldAsLoad = 1 in 171 def MMX_MOVQ64rm : MMXI<0x6F, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src), 172 "movq\t{$src, $dst|$dst, $src}", 173 [(set VR64:$dst, (load_mmx addr:$src))]>; 174 def MMX_MOVQ64mr : MMXI<0x7F, MRMDestMem, (outs), (ins i64mem:$dst, VR64:$src), 175 "movq\t{$src, $dst|$dst, $src}", 176 [(store (x86mmx VR64:$src), addr:$dst)]>; 177 178 def MMX_MOVDQ2Qrr : SDIi8<0xD6, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src), 179 "movdq2q\t{$src, $dst|$dst, $src}", 180 [(set VR64:$dst, 181 (x86mmx (bitconvert 182 (i64 (vector_extract (v2i64 VR128:$src), 183 (iPTR 0))))))]>; 184 185 def MMX_MOVQ2DQrr : SSDIi8<0xD6, MRMSrcReg, (outs VR128:$dst), (ins VR64:$src), 186 "movq2dq\t{$src, $dst|$dst, $src}", 187 [(set VR128:$dst, 188 (v2i64 (scalar_to_vector 189 (i64 (bitconvert (x86mmx VR64:$src))))))]>; 190 191 let neverHasSideEffects = 1 in 192 def MMX_MOVQ2FR64rr: SSDIi8<0xD6, MRMSrcReg, (outs FR64:$dst), (ins VR64:$src), 193 "movq2dq\t{$src, $dst|$dst, $src}", []>; 194 195 def MMX_MOVFR642Qrr: SDIi8<0xD6, MRMSrcReg, (outs VR64:$dst), (ins FR64:$src), 196 "movdq2q\t{$src, $dst|$dst, $src}", []>; 197 198 def MMX_MOVNTQmr : MMXI<0xE7, MRMDestMem, (outs), (ins i64mem:$dst, VR64:$src), 199 "movntq\t{$src, $dst|$dst, $src}", 200 [(int_x86_mmx_movnt_dq addr:$dst, VR64:$src)]>; 201 202 let AddedComplexity = 15 in 203 // movd to MMX register zero-extends 204 def MMX_MOVZDI2PDIrr : MMXI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR32:$src), 205 "movd\t{$src, $dst|$dst, $src}", 206 [(set VR64:$dst, 207 (x86mmx (X86vzmovl (x86mmx (scalar_to_vector GR32:$src)))))]>; 208 let AddedComplexity = 20 in 209 def MMX_MOVZDI2PDIrm : MMXI<0x6E, MRMSrcMem, (outs VR64:$dst), 210 (ins i32mem:$src), 211 "movd\t{$src, $dst|$dst, $src}", 212 [(set VR64:$dst, 213 (x86mmx (X86vzmovl (x86mmx 214 (scalar_to_vector (loadi32 addr:$src))))))]>; 215 216 // Arithmetic Instructions 217 defm MMX_PABSB : SS3I_unop_rm_int_mm<0x1C, "pabsb", int_x86_ssse3_pabs_b>; 218 defm MMX_PABSW : SS3I_unop_rm_int_mm<0x1D, "pabsw", int_x86_ssse3_pabs_w>; 219 defm MMX_PABSD : SS3I_unop_rm_int_mm<0x1E, "pabsd", int_x86_ssse3_pabs_d>; 220 // -- Addition 221 defm MMX_PADDB : MMXI_binop_rm_int<0xFC, "paddb", int_x86_mmx_padd_b, 1>; 222 defm MMX_PADDW : MMXI_binop_rm_int<0xFD, "paddw", int_x86_mmx_padd_w, 1>; 223 defm MMX_PADDD : MMXI_binop_rm_int<0xFE, "paddd", int_x86_mmx_padd_d, 1>; 224 defm MMX_PADDQ : MMXI_binop_rm_int<0xD4, "paddq", int_x86_mmx_padd_q, 1>; 225 defm MMX_PADDSB : MMXI_binop_rm_int<0xEC, "paddsb" , int_x86_mmx_padds_b, 1>; 226 defm MMX_PADDSW : MMXI_binop_rm_int<0xED, "paddsw" , int_x86_mmx_padds_w, 1>; 227 228 defm MMX_PADDUSB : MMXI_binop_rm_int<0xDC, "paddusb", int_x86_mmx_paddus_b, 1>; 229 defm MMX_PADDUSW : MMXI_binop_rm_int<0xDD, "paddusw", int_x86_mmx_paddus_w, 1>; 230 231 defm MMX_PHADDW : SS3I_binop_rm_int_mm<0x01, "phaddw", int_x86_ssse3_phadd_w>; 232 defm MMX_PHADD : SS3I_binop_rm_int_mm<0x02, "phaddd", int_x86_ssse3_phadd_d>; 233 defm MMX_PHADDSW : SS3I_binop_rm_int_mm<0x03, "phaddsw",int_x86_ssse3_phadd_sw>; 234 235 236 // -- Subtraction 237 defm MMX_PSUBB : MMXI_binop_rm_int<0xF8, "psubb", int_x86_mmx_psub_b>; 238 defm MMX_PSUBW : MMXI_binop_rm_int<0xF9, "psubw", int_x86_mmx_psub_w>; 239 defm MMX_PSUBD : MMXI_binop_rm_int<0xFA, "psubd", int_x86_mmx_psub_d>; 240 defm MMX_PSUBQ : MMXI_binop_rm_int<0xFB, "psubq", int_x86_mmx_psub_q>; 241 242 defm MMX_PSUBSB : MMXI_binop_rm_int<0xE8, "psubsb" , int_x86_mmx_psubs_b>; 243 defm MMX_PSUBSW : MMXI_binop_rm_int<0xE9, "psubsw" , int_x86_mmx_psubs_w>; 244 245 defm MMX_PSUBUSB : MMXI_binop_rm_int<0xD8, "psubusb", int_x86_mmx_psubus_b>; 246 defm MMX_PSUBUSW : MMXI_binop_rm_int<0xD9, "psubusw", int_x86_mmx_psubus_w>; 247 248 defm MMX_PHSUBW : SS3I_binop_rm_int_mm<0x05, "phsubw", int_x86_ssse3_phsub_w>; 249 defm MMX_PHSUBD : SS3I_binop_rm_int_mm<0x06, "phsubd", int_x86_ssse3_phsub_d>; 250 defm MMX_PHSUBSW : SS3I_binop_rm_int_mm<0x07, "phsubsw",int_x86_ssse3_phsub_sw>; 251 252 // -- Multiplication 253 defm MMX_PMULLW : MMXI_binop_rm_int<0xD5, "pmullw", int_x86_mmx_pmull_w, 1>; 254 255 defm MMX_PMULHW : MMXI_binop_rm_int<0xE5, "pmulhw", int_x86_mmx_pmulh_w, 1>; 256 defm MMX_PMULHUW : MMXI_binop_rm_int<0xE4, "pmulhuw", int_x86_mmx_pmulhu_w, 1>; 257 defm MMX_PMULUDQ : MMXI_binop_rm_int<0xF4, "pmuludq", int_x86_mmx_pmulu_dq, 1>; 258 let isCommutable = 1 in 259 defm MMX_PMULHRSW : SS3I_binop_rm_int_mm<0x0B, "pmulhrsw", 260 int_x86_ssse3_pmul_hr_sw>; 261 262 // -- Miscellanea 263 defm MMX_PMADDWD : MMXI_binop_rm_int<0xF5, "pmaddwd", int_x86_mmx_pmadd_wd, 1>; 264 265 defm MMX_PMADDUBSW : SS3I_binop_rm_int_mm<0x04, "pmaddubsw", 266 int_x86_ssse3_pmadd_ub_sw>; 267 defm MMX_PAVGB : MMXI_binop_rm_int<0xE0, "pavgb", int_x86_mmx_pavg_b, 1>; 268 defm MMX_PAVGW : MMXI_binop_rm_int<0xE3, "pavgw", int_x86_mmx_pavg_w, 1>; 269 270 defm MMX_PMINUB : MMXI_binop_rm_int<0xDA, "pminub", int_x86_mmx_pminu_b, 1>; 271 defm MMX_PMINSW : MMXI_binop_rm_int<0xEA, "pminsw", int_x86_mmx_pmins_w, 1>; 272 273 defm MMX_PMAXUB : MMXI_binop_rm_int<0xDE, "pmaxub", int_x86_mmx_pmaxu_b, 1>; 274 defm MMX_PMAXSW : MMXI_binop_rm_int<0xEE, "pmaxsw", int_x86_mmx_pmaxs_w, 1>; 275 276 defm MMX_PSADBW : MMXI_binop_rm_int<0xF6, "psadbw", int_x86_mmx_psad_bw, 1>; 277 278 defm MMX_PSIGNB : SS3I_binop_rm_int_mm<0x08, "psignb", int_x86_ssse3_psign_b>; 279 defm MMX_PSIGNW : SS3I_binop_rm_int_mm<0x09, "psignw", int_x86_ssse3_psign_w>; 280 defm MMX_PSIGND : SS3I_binop_rm_int_mm<0x0A, "psignd", int_x86_ssse3_psign_d>; 281 let Constraints = "$src1 = $dst" in 282 defm MMX_PALIGN : ssse3_palign_mm<"palignr", int_x86_mmx_palignr_b>; 283 284 // Logical Instructions 285 defm MMX_PAND : MMXI_binop_rm_int<0xDB, "pand", int_x86_mmx_pand, 1>; 286 defm MMX_POR : MMXI_binop_rm_int<0xEB, "por" , int_x86_mmx_por, 1>; 287 defm MMX_PXOR : MMXI_binop_rm_int<0xEF, "pxor", int_x86_mmx_pxor, 1>; 288 defm MMX_PANDN : MMXI_binop_rm_int<0xDF, "pandn", int_x86_mmx_pandn>; 289 290 // Shift Instructions 291 defm MMX_PSRLW : MMXI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw", 292 int_x86_mmx_psrl_w, int_x86_mmx_psrli_w>; 293 defm MMX_PSRLD : MMXI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld", 294 int_x86_mmx_psrl_d, int_x86_mmx_psrli_d>; 295 defm MMX_PSRLQ : MMXI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq", 296 int_x86_mmx_psrl_q, int_x86_mmx_psrli_q>; 297 298 defm MMX_PSLLW : MMXI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw", 299 int_x86_mmx_psll_w, int_x86_mmx_pslli_w>; 300 defm MMX_PSLLD : MMXI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld", 301 int_x86_mmx_psll_d, int_x86_mmx_pslli_d>; 302 defm MMX_PSLLQ : MMXI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq", 303 int_x86_mmx_psll_q, int_x86_mmx_pslli_q>; 304 305 defm MMX_PSRAW : MMXI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw", 306 int_x86_mmx_psra_w, int_x86_mmx_psrai_w>; 307 defm MMX_PSRAD : MMXI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad", 308 int_x86_mmx_psra_d, int_x86_mmx_psrai_d>; 309 310 // Comparison Instructions 311 defm MMX_PCMPEQB : MMXI_binop_rm_int<0x74, "pcmpeqb", int_x86_mmx_pcmpeq_b>; 312 defm MMX_PCMPEQW : MMXI_binop_rm_int<0x75, "pcmpeqw", int_x86_mmx_pcmpeq_w>; 313 defm MMX_PCMPEQD : MMXI_binop_rm_int<0x76, "pcmpeqd", int_x86_mmx_pcmpeq_d>; 314 315 defm MMX_PCMPGTB : MMXI_binop_rm_int<0x64, "pcmpgtb", int_x86_mmx_pcmpgt_b>; 316 defm MMX_PCMPGTW : MMXI_binop_rm_int<0x65, "pcmpgtw", int_x86_mmx_pcmpgt_w>; 317 defm MMX_PCMPGTD : MMXI_binop_rm_int<0x66, "pcmpgtd", int_x86_mmx_pcmpgt_d>; 318 319 // -- Unpack Instructions 320 defm MMX_PUNPCKHBW : MMXI_binop_rm_int<0x68, "punpckhbw", 321 int_x86_mmx_punpckhbw>; 322 defm MMX_PUNPCKHWD : MMXI_binop_rm_int<0x69, "punpckhwd", 323 int_x86_mmx_punpckhwd>; 324 defm MMX_PUNPCKHDQ : MMXI_binop_rm_int<0x6A, "punpckhdq", 325 int_x86_mmx_punpckhdq>; 326 defm MMX_PUNPCKLBW : MMXI_binop_rm_int<0x60, "punpcklbw", 327 int_x86_mmx_punpcklbw>; 328 defm MMX_PUNPCKLWD : MMXI_binop_rm_int<0x61, "punpcklwd", 329 int_x86_mmx_punpcklwd>; 330 defm MMX_PUNPCKLDQ : MMXI_binop_rm_int<0x62, "punpckldq", 331 int_x86_mmx_punpckldq>; 332 333 // -- Pack Instructions 334 defm MMX_PACKSSWB : MMXI_binop_rm_int<0x63, "packsswb", int_x86_mmx_packsswb>; 335 defm MMX_PACKSSDW : MMXI_binop_rm_int<0x6B, "packssdw", int_x86_mmx_packssdw>; 336 defm MMX_PACKUSWB : MMXI_binop_rm_int<0x67, "packuswb", int_x86_mmx_packuswb>; 337 338 // -- Shuffle Instructions 339 defm MMX_PSHUFB : SS3I_binop_rm_int_mm<0x00, "pshufb", int_x86_ssse3_pshuf_b>; 340 341 def MMX_PSHUFWri : MMXIi8<0x70, MRMSrcReg, 342 (outs VR64:$dst), (ins VR64:$src1, i8imm:$src2), 343 "pshufw\t{$src2, $src1, $dst|$dst, $src1, $src2}", 344 [(set VR64:$dst, 345 (int_x86_sse_pshuf_w VR64:$src1, imm:$src2))]>; 346 def MMX_PSHUFWmi : MMXIi8<0x70, MRMSrcMem, 347 (outs VR64:$dst), (ins i64mem:$src1, i8imm:$src2), 348 "pshufw\t{$src2, $src1, $dst|$dst, $src1, $src2}", 349 [(set VR64:$dst, 350 (int_x86_sse_pshuf_w (load_mmx addr:$src1), 351 imm:$src2))]>; 352 353 354 355 356 357 // -- Conversion Instructions 358 defm MMX_CVTPS2PI : sse12_cvt_pint<0x2D, VR128, VR64, int_x86_sse_cvtps2pi, 359 f64mem, load, "cvtps2pi\t{$src, $dst|$dst, $src}", 360 SSEPackedSingle>, TB; 361 defm MMX_CVTPD2PI : sse12_cvt_pint<0x2D, VR128, VR64, int_x86_sse_cvtpd2pi, 362 f128mem, memop, "cvtpd2pi\t{$src, $dst|$dst, $src}", 363 SSEPackedDouble>, TB, OpSize; 364 defm MMX_CVTTPS2PI : sse12_cvt_pint<0x2C, VR128, VR64, int_x86_sse_cvttps2pi, 365 f64mem, load, "cvttps2pi\t{$src, $dst|$dst, $src}", 366 SSEPackedSingle>, TB; 367 defm MMX_CVTTPD2PI : sse12_cvt_pint<0x2C, VR128, VR64, int_x86_sse_cvttpd2pi, 368 f128mem, memop, "cvttpd2pi\t{$src, $dst|$dst, $src}", 369 SSEPackedDouble>, TB, OpSize; 370 defm MMX_CVTPI2PD : sse12_cvt_pint<0x2A, VR64, VR128, int_x86_sse_cvtpi2pd, 371 i64mem, load, "cvtpi2pd\t{$src, $dst|$dst, $src}", 372 SSEPackedDouble>, TB, OpSize; 373 let Constraints = "$src1 = $dst" in { 374 defm MMX_CVTPI2PS : sse12_cvt_pint_3addr<0x2A, VR64, VR128, 375 int_x86_sse_cvtpi2ps, 376 i64mem, load, "cvtpi2ps\t{$src2, $dst|$dst, $src2}", 377 SSEPackedSingle>, TB; 378 } 379 380 // Extract / Insert 381 def MMX_PEXTRWirri: MMXIi8<0xC5, MRMSrcReg, 382 (outs GR32:$dst), (ins VR64:$src1, i32i8imm:$src2), 383 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}", 384 [(set GR32:$dst, (int_x86_mmx_pextr_w VR64:$src1, 385 (iPTR imm:$src2)))]>; 386 let Constraints = "$src1 = $dst" in { 387 def MMX_PINSRWirri : MMXIi8<0xC4, MRMSrcReg, 388 (outs VR64:$dst), 389 (ins VR64:$src1, GR32:$src2, i32i8imm:$src3), 390 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}", 391 [(set VR64:$dst, (int_x86_mmx_pinsr_w VR64:$src1, 392 GR32:$src2, (iPTR imm:$src3)))]>; 393 394 def MMX_PINSRWirmi : MMXIi8<0xC4, MRMSrcMem, 395 (outs VR64:$dst), 396 (ins VR64:$src1, i16mem:$src2, i32i8imm:$src3), 397 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}", 398 [(set VR64:$dst, (int_x86_mmx_pinsr_w VR64:$src1, 399 (i32 (anyext (loadi16 addr:$src2))), 400 (iPTR imm:$src3)))]>; 401 } 402 403 // Mask creation 404 def MMX_PMOVMSKBrr : MMXI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR64:$src), 405 "pmovmskb\t{$src, $dst|$dst, $src}", 406 [(set GR32:$dst, 407 (int_x86_mmx_pmovmskb VR64:$src))]>; 408 409 410 // MMX to XMM for vector types 411 def MMX_X86movq2dq : SDNode<"X86ISD::MOVQ2DQ", SDTypeProfile<1, 1, 412 [SDTCisVT<0, v2i64>, SDTCisVT<1, x86mmx>]>>; 413 414 def : Pat<(v2i64 (MMX_X86movq2dq VR64:$src)), 415 (v2i64 (MMX_MOVQ2DQrr VR64:$src))>; 416 417 def : Pat<(v2i64 (MMX_X86movq2dq (load_mmx addr:$src))), 418 (v2i64 (MOVQI2PQIrm addr:$src))>; 419 420 def : Pat<(v2i64 (MMX_X86movq2dq 421 (x86mmx (scalar_to_vector (loadi32 addr:$src))))), 422 (v2i64 (MOVDI2PDIrm addr:$src))>; 423 424 // Low word of XMM to MMX. 425 def MMX_X86movdq2q : SDNode<"X86ISD::MOVDQ2Q", SDTypeProfile<1, 1, 426 [SDTCisVT<0, x86mmx>, SDTCisVT<1, v2i64>]>>; 427 428 def : Pat<(x86mmx (MMX_X86movdq2q VR128:$src)), 429 (x86mmx (MMX_MOVDQ2Qrr VR128:$src))>; 430 431 def : Pat<(x86mmx (MMX_X86movdq2q (loadv2i64 addr:$src))), 432 (x86mmx (MMX_MOVQ64rm addr:$src))>; 433 434 // Misc. 435 let Uses = [EDI] in 436 def MMX_MASKMOVQ : MMXI<0xF7, MRMSrcReg, (outs), (ins VR64:$src, VR64:$mask), 437 "maskmovq\t{$mask, $src|$src, $mask}", 438 [(int_x86_mmx_maskmovq VR64:$src, VR64:$mask, EDI)]>; 439 let Uses = [RDI] in 440 def MMX_MASKMOVQ64: MMXI64<0xF7, MRMSrcReg, (outs), (ins VR64:$src, VR64:$mask), 441 "maskmovq\t{$mask, $src|$src, $mask}", 442 [(int_x86_mmx_maskmovq VR64:$src, VR64:$mask, RDI)]>; 443 444 // 64-bit bit convert. 445 def : Pat<(x86mmx (bitconvert (i64 GR64:$src))), 446 (MMX_MOVD64to64rr GR64:$src)>; 447 def : Pat<(i64 (bitconvert (x86mmx VR64:$src))), 448 (MMX_MOVD64from64rr VR64:$src)>; 449 def : Pat<(f64 (bitconvert (x86mmx VR64:$src))), 450 (MMX_MOVQ2FR64rr VR64:$src)>; 451 def : Pat<(x86mmx (bitconvert (f64 FR64:$src))), 452 (MMX_MOVFR642Qrr FR64:$src)>; 453 454 455
