1 //===- XCore.td - Describe the XCore Target Machine --------*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // 11 //===----------------------------------------------------------------------===// 12 13 //===----------------------------------------------------------------------===// 14 // Target-independent interfaces which we are implementing 15 //===----------------------------------------------------------------------===// 16 17 include "llvm/Target/Target.td" 18 19 //===----------------------------------------------------------------------===// 20 // Descriptions 21 //===----------------------------------------------------------------------===// 22 23 include "XCoreRegisterInfo.td" 24 include "XCoreInstrInfo.td" 25 include "XCoreCallingConv.td" 26 27 def XCoreInstrInfo : InstrInfo; 28 29 //===----------------------------------------------------------------------===// 30 // XCore processors supported. 31 //===----------------------------------------------------------------------===// 32 33 class Proc<string Name, list<SubtargetFeature> Features> 34 : Processor<Name, NoItineraries, Features>; 35 36 def : Proc<"generic", []>; 37 def : Proc<"xs1b-generic", []>; 38 39 //===----------------------------------------------------------------------===// 40 // Declare the target which we are implementing 41 //===----------------------------------------------------------------------===// 42 43 def XCore : Target { 44 // Pull in Instruction Info: 45 let InstructionSet = XCoreInstrInfo; 46 } 47
