1 ; RUN: llc < %s -mtriple=arm-apple-darwin -mattr=+v6,+vfp2 | FileCheck %s 2 3 @quant_coef = external global [6 x [4 x [4 x i32]]] ; <[6 x [4 x [4 x i32]]]*> [#uses=1] 4 @dequant_coef = external global [6 x [4 x [4 x i32]]] ; <[6 x [4 x [4 x i32]]]*> [#uses=1] 5 @A = external global [4 x [4 x i32]] ; <[4 x [4 x i32]]*> [#uses=1] 6 7 ; CHECK: dct_luma_sp: 8 define fastcc i32 @dct_luma_sp(i32 %block_x, i32 %block_y, i32* %coeff_cost) { 9 entry: 10 ; Make sure to use base-updating stores for saving callee-saved registers. 11 ; CHECK: push 12 ; CHECK-NOT: sub sp 13 ; CHECK: push 14 %predicted_block = alloca [4 x [4 x i32]], align 4 ; <[4 x [4 x i32]]*> [#uses=1] 15 br label %cond_next489 16 17 cond_next489: ; preds = %cond_false, %bb471 18 %j.7.in = load i8* null ; <i8> [#uses=1] 19 %i.8.in = load i8* null ; <i8> [#uses=1] 20 %i.8 = zext i8 %i.8.in to i32 ; <i32> [#uses=4] 21 %j.7 = zext i8 %j.7.in to i32 ; <i32> [#uses=4] 22 %tmp495 = getelementptr [4 x [4 x i32]]* %predicted_block, i32 0, i32 %i.8, i32 %j.7 ; <i32*> [#uses=2] 23 %tmp496 = load i32* %tmp495 ; <i32> [#uses=2] 24 %tmp502 = load i32* null ; <i32> [#uses=1] 25 %tmp542 = getelementptr [6 x [4 x [4 x i32]]]* @quant_coef, i32 0, i32 0, i32 %i.8, i32 %j.7 ; <i32*> [#uses=1] 26 %tmp543 = load i32* %tmp542 ; <i32> [#uses=1] 27 %tmp548 = ashr i32 0, 0 ; <i32> [#uses=3] 28 %tmp561 = sub i32 0, %tmp496 ; <i32> [#uses=3] 29 %abscond563 = icmp sgt i32 %tmp561, -1 ; <i1> [#uses=1] 30 %abs564 = select i1 %abscond563, i32 %tmp561, i32 0 ; <i32> [#uses=1] 31 %tmp572 = mul i32 %abs564, %tmp543 ; <i32> [#uses=1] 32 %tmp574 = add i32 %tmp572, 0 ; <i32> [#uses=1] 33 %tmp576 = ashr i32 %tmp574, 0 ; <i32> [#uses=7] 34 %tmp579 = icmp eq i32 %tmp548, %tmp576 ; <i1> [#uses=1] 35 br i1 %tmp579, label %bb712, label %cond_next589 36 37 cond_next589: ; preds = %cond_next489 38 %tmp605 = getelementptr [6 x [4 x [4 x i32]]]* @dequant_coef, i32 0, i32 0, i32 %i.8, i32 %j.7 ; <i32*> [#uses=1] 39 %tmp606 = load i32* %tmp605 ; <i32> [#uses=1] 40 %tmp612 = load i32* null ; <i32> [#uses=1] 41 %tmp629 = load i32* null ; <i32> [#uses=1] 42 %tmp629a = sitofp i32 %tmp629 to double ; <double> [#uses=1] 43 %tmp631 = fmul double %tmp629a, 0.000000e+00 ; <double> [#uses=1] 44 %tmp632 = fadd double 0.000000e+00, %tmp631 ; <double> [#uses=1] 45 %tmp642 = call fastcc i32 @sign( i32 %tmp576, i32 %tmp561 ) ; <i32> [#uses=1] 46 %tmp650 = mul i32 %tmp606, %tmp642 ; <i32> [#uses=1] 47 %tmp656 = mul i32 %tmp650, %tmp612 ; <i32> [#uses=1] 48 %tmp658 = shl i32 %tmp656, 0 ; <i32> [#uses=1] 49 %tmp659 = ashr i32 %tmp658, 6 ; <i32> [#uses=1] 50 %tmp660 = sub i32 0, %tmp659 ; <i32> [#uses=1] 51 %tmp666 = sub i32 %tmp660, %tmp496 ; <i32> [#uses=1] 52 %tmp667 = sitofp i32 %tmp666 to double ; <double> [#uses=2] 53 call void @levrun_linfo_inter( i32 %tmp576, i32 0, i32* null, i32* null ) 54 %tmp671 = fmul double %tmp667, %tmp667 ; <double> [#uses=1] 55 %tmp675 = fadd double %tmp671, 0.000000e+00 ; <double> [#uses=1] 56 %tmp678 = fcmp oeq double %tmp632, %tmp675 ; <i1> [#uses=1] 57 br i1 %tmp678, label %cond_true679, label %cond_false693 58 59 cond_true679: ; preds = %cond_next589 60 %abscond681 = icmp sgt i32 %tmp548, -1 ; <i1> [#uses=1] 61 %abs682 = select i1 %abscond681, i32 %tmp548, i32 0 ; <i32> [#uses=1] 62 %abscond684 = icmp sgt i32 %tmp576, -1 ; <i1> [#uses=1] 63 %abs685 = select i1 %abscond684, i32 %tmp576, i32 0 ; <i32> [#uses=1] 64 %tmp686 = icmp slt i32 %abs682, %abs685 ; <i1> [#uses=1] 65 br i1 %tmp686, label %cond_next702, label %cond_false689 66 67 cond_false689: ; preds = %cond_true679 68 %tmp739 = icmp eq i32 %tmp576, 0 ; <i1> [#uses=1] 69 br i1 %tmp579, label %bb737, label %cond_false708 70 71 cond_false693: ; preds = %cond_next589 72 ret i32 0 73 74 cond_next702: ; preds = %cond_true679 75 ret i32 0 76 77 cond_false708: ; preds = %cond_false689 78 ret i32 0 79 80 bb712: ; preds = %cond_next489 81 ret i32 0 82 83 bb737: ; preds = %cond_false689 84 br i1 %tmp739, label %cond_next791, label %cond_true740 85 86 cond_true740: ; preds = %bb737 87 %tmp761 = call fastcc i32 @sign( i32 %tmp576, i32 0 ) ; <i32> [#uses=1] 88 %tmp780 = load i32* null ; <i32> [#uses=1] 89 %tmp785 = getelementptr [4 x [4 x i32]]* @A, i32 0, i32 %i.8, i32 %j.7 ; <i32*> [#uses=1] 90 %tmp786 = load i32* %tmp785 ; <i32> [#uses=1] 91 %tmp781 = mul i32 %tmp780, %tmp761 ; <i32> [#uses=1] 92 %tmp787 = mul i32 %tmp781, %tmp786 ; <i32> [#uses=1] 93 %tmp789 = shl i32 %tmp787, 0 ; <i32> [#uses=1] 94 %tmp790 = ashr i32 %tmp789, 6 ; <i32> [#uses=1] 95 br label %cond_next791 96 97 cond_next791: ; preds = %cond_true740, %bb737 98 %ilev.1 = phi i32 [ %tmp790, %cond_true740 ], [ 0, %bb737 ] ; <i32> [#uses=1] 99 %tmp796 = load i32* %tmp495 ; <i32> [#uses=1] 100 %tmp798 = add i32 %tmp796, %ilev.1 ; <i32> [#uses=1] 101 %tmp812 = mul i32 0, %tmp502 ; <i32> [#uses=0] 102 %tmp818 = call fastcc i32 @sign( i32 0, i32 %tmp798 ) ; <i32> [#uses=0] 103 unreachable 104 } 105 106 declare i32 @sign(i32, i32) 107 108 declare void @levrun_linfo_inter(i32, i32, i32*, i32*) 109
