1 ; RUN: llc < %s -mtriple=armv7-apple-darwin | FileCheck %s 2 ; PHI elimination shouldn't break backedge. 3 ; rdar://8263994 4 5 %struct.list_data_s = type { i16, i16 } 6 %struct.list_head = type { %struct.list_head*, %struct.list_data_s* } 7 8 define arm_apcscc %struct.list_head* @t1(%struct.list_head* %list) nounwind { 9 entry: 10 ; CHECK: t1: 11 %0 = icmp eq %struct.list_head* %list, null 12 br i1 %0, label %bb2, label %bb 13 14 bb: 15 ; CHECK: LBB0_2: 16 ; CHECK: bne LBB0_2 17 ; CHECK-NOT: b LBB0_2 18 ; CHECK: bx lr 19 %list_addr.05 = phi %struct.list_head* [ %2, %bb ], [ %list, %entry ] 20 %next.04 = phi %struct.list_head* [ %list_addr.05, %bb ], [ null, %entry ] 21 %1 = getelementptr inbounds %struct.list_head* %list_addr.05, i32 0, i32 0 22 %2 = load %struct.list_head** %1, align 4 23 store %struct.list_head* %next.04, %struct.list_head** %1, align 4 24 %3 = icmp eq %struct.list_head* %2, null 25 br i1 %3, label %bb2, label %bb 26 27 bb2: 28 %next.0.lcssa = phi %struct.list_head* [ null, %entry ], [ %list_addr.05, %bb ] 29 ret %struct.list_head* %next.0.lcssa 30 } 31 32 ; Optimize loop entry, eliminate intra loop branches 33 ; rdar://8117827 34 define i32 @t2(i32 %passes, i32* nocapture %src, i32 %size) nounwind readonly { 35 entry: 36 ; CHECK: t2: 37 ; CHECK: beq LBB1_[[RET:.]] 38 %0 = icmp eq i32 %passes, 0 ; <i1> [#uses=1] 39 br i1 %0, label %bb5, label %bb.nph15 40 41 ; CHECK: LBB1_[[PREHDR:.]]: @ %bb2.preheader 42 bb1: ; preds = %bb2.preheader, %bb1 43 ; CHECK: LBB1_[[BB1:.]]: @ %bb1 44 ; CHECK: bne LBB1_[[BB1]] 45 %indvar = phi i32 [ %indvar.next, %bb1 ], [ 0, %bb2.preheader ] ; <i32> [#uses=2] 46 %sum.08 = phi i32 [ %2, %bb1 ], [ %sum.110, %bb2.preheader ] ; <i32> [#uses=1] 47 %tmp17 = sub i32 %i.07, %indvar ; <i32> [#uses=1] 48 %scevgep = getelementptr i32* %src, i32 %tmp17 ; <i32*> [#uses=1] 49 %1 = load i32* %scevgep, align 4 ; <i32> [#uses=1] 50 %2 = add nsw i32 %1, %sum.08 ; <i32> [#uses=2] 51 %indvar.next = add i32 %indvar, 1 ; <i32> [#uses=2] 52 %exitcond = icmp eq i32 %indvar.next, %size ; <i1> [#uses=1] 53 br i1 %exitcond, label %bb3, label %bb1 54 55 bb3: ; preds = %bb1, %bb2.preheader 56 ; CHECK: LBB1_[[BB3:.]]: @ %bb3 57 ; CHECK: bne LBB1_[[PREHDR]] 58 ; CHECK-NOT: b LBB1_ 59 %sum.0.lcssa = phi i32 [ %sum.110, %bb2.preheader ], [ %2, %bb1 ] ; <i32> [#uses=2] 60 %3 = add i32 %pass.011, 1 ; <i32> [#uses=2] 61 %exitcond18 = icmp eq i32 %3, %passes ; <i1> [#uses=1] 62 br i1 %exitcond18, label %bb5, label %bb2.preheader 63 64 bb.nph15: ; preds = %entry 65 %i.07 = add i32 %size, -1 ; <i32> [#uses=2] 66 %4 = icmp sgt i32 %i.07, -1 ; <i1> [#uses=1] 67 br label %bb2.preheader 68 69 bb2.preheader: ; preds = %bb3, %bb.nph15 70 %pass.011 = phi i32 [ 0, %bb.nph15 ], [ %3, %bb3 ] ; <i32> [#uses=1] 71 %sum.110 = phi i32 [ 0, %bb.nph15 ], [ %sum.0.lcssa, %bb3 ] ; <i32> [#uses=2] 72 br i1 %4, label %bb1, label %bb3 73 74 ; CHECK: LBB1_[[RET]]: @ %bb5 75 ; CHECK: pop 76 bb5: ; preds = %bb3, %entry 77 %sum.1.lcssa = phi i32 [ 0, %entry ], [ %sum.0.lcssa, %bb3 ] ; <i32> [#uses=1] 78 ret i32 %sum.1.lcssa 79 } 80
