1 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s 2 3 define <8 x i8> @vabss8(<8 x i8>* %A) nounwind { 4 ;CHECK: vabss8: 5 ;CHECK: vabs.s8 6 %tmp1 = load <8 x i8>* %A 7 %tmp2 = call <8 x i8> @llvm.arm.neon.vabs.v8i8(<8 x i8> %tmp1) 8 ret <8 x i8> %tmp2 9 } 10 11 define <4 x i16> @vabss16(<4 x i16>* %A) nounwind { 12 ;CHECK: vabss16: 13 ;CHECK: vabs.s16 14 %tmp1 = load <4 x i16>* %A 15 %tmp2 = call <4 x i16> @llvm.arm.neon.vabs.v4i16(<4 x i16> %tmp1) 16 ret <4 x i16> %tmp2 17 } 18 19 define <2 x i32> @vabss32(<2 x i32>* %A) nounwind { 20 ;CHECK: vabss32: 21 ;CHECK: vabs.s32 22 %tmp1 = load <2 x i32>* %A 23 %tmp2 = call <2 x i32> @llvm.arm.neon.vabs.v2i32(<2 x i32> %tmp1) 24 ret <2 x i32> %tmp2 25 } 26 27 define <2 x float> @vabsf32(<2 x float>* %A) nounwind { 28 ;CHECK: vabsf32: 29 ;CHECK: vabs.f32 30 %tmp1 = load <2 x float>* %A 31 %tmp2 = call <2 x float> @llvm.arm.neon.vabs.v2f32(<2 x float> %tmp1) 32 ret <2 x float> %tmp2 33 } 34 35 define <16 x i8> @vabsQs8(<16 x i8>* %A) nounwind { 36 ;CHECK: vabsQs8: 37 ;CHECK: vabs.s8 38 %tmp1 = load <16 x i8>* %A 39 %tmp2 = call <16 x i8> @llvm.arm.neon.vabs.v16i8(<16 x i8> %tmp1) 40 ret <16 x i8> %tmp2 41 } 42 43 define <8 x i16> @vabsQs16(<8 x i16>* %A) nounwind { 44 ;CHECK: vabsQs16: 45 ;CHECK: vabs.s16 46 %tmp1 = load <8 x i16>* %A 47 %tmp2 = call <8 x i16> @llvm.arm.neon.vabs.v8i16(<8 x i16> %tmp1) 48 ret <8 x i16> %tmp2 49 } 50 51 define <4 x i32> @vabsQs32(<4 x i32>* %A) nounwind { 52 ;CHECK: vabsQs32: 53 ;CHECK: vabs.s32 54 %tmp1 = load <4 x i32>* %A 55 %tmp2 = call <4 x i32> @llvm.arm.neon.vabs.v4i32(<4 x i32> %tmp1) 56 ret <4 x i32> %tmp2 57 } 58 59 define <4 x float> @vabsQf32(<4 x float>* %A) nounwind { 60 ;CHECK: vabsQf32: 61 ;CHECK: vabs.f32 62 %tmp1 = load <4 x float>* %A 63 %tmp2 = call <4 x float> @llvm.arm.neon.vabs.v4f32(<4 x float> %tmp1) 64 ret <4 x float> %tmp2 65 } 66 67 declare <8 x i8> @llvm.arm.neon.vabs.v8i8(<8 x i8>) nounwind readnone 68 declare <4 x i16> @llvm.arm.neon.vabs.v4i16(<4 x i16>) nounwind readnone 69 declare <2 x i32> @llvm.arm.neon.vabs.v2i32(<2 x i32>) nounwind readnone 70 declare <2 x float> @llvm.arm.neon.vabs.v2f32(<2 x float>) nounwind readnone 71 72 declare <16 x i8> @llvm.arm.neon.vabs.v16i8(<16 x i8>) nounwind readnone 73 declare <8 x i16> @llvm.arm.neon.vabs.v8i16(<8 x i16>) nounwind readnone 74 declare <4 x i32> @llvm.arm.neon.vabs.v4i32(<4 x i32>) nounwind readnone 75 declare <4 x float> @llvm.arm.neon.vabs.v4f32(<4 x float>) nounwind readnone 76 77 define <8 x i8> @vqabss8(<8 x i8>* %A) nounwind { 78 ;CHECK: vqabss8: 79 ;CHECK: vqabs.s8 80 %tmp1 = load <8 x i8>* %A 81 %tmp2 = call <8 x i8> @llvm.arm.neon.vqabs.v8i8(<8 x i8> %tmp1) 82 ret <8 x i8> %tmp2 83 } 84 85 define <4 x i16> @vqabss16(<4 x i16>* %A) nounwind { 86 ;CHECK: vqabss16: 87 ;CHECK: vqabs.s16 88 %tmp1 = load <4 x i16>* %A 89 %tmp2 = call <4 x i16> @llvm.arm.neon.vqabs.v4i16(<4 x i16> %tmp1) 90 ret <4 x i16> %tmp2 91 } 92 93 define <2 x i32> @vqabss32(<2 x i32>* %A) nounwind { 94 ;CHECK: vqabss32: 95 ;CHECK: vqabs.s32 96 %tmp1 = load <2 x i32>* %A 97 %tmp2 = call <2 x i32> @llvm.arm.neon.vqabs.v2i32(<2 x i32> %tmp1) 98 ret <2 x i32> %tmp2 99 } 100 101 define <16 x i8> @vqabsQs8(<16 x i8>* %A) nounwind { 102 ;CHECK: vqabsQs8: 103 ;CHECK: vqabs.s8 104 %tmp1 = load <16 x i8>* %A 105 %tmp2 = call <16 x i8> @llvm.arm.neon.vqabs.v16i8(<16 x i8> %tmp1) 106 ret <16 x i8> %tmp2 107 } 108 109 define <8 x i16> @vqabsQs16(<8 x i16>* %A) nounwind { 110 ;CHECK: vqabsQs16: 111 ;CHECK: vqabs.s16 112 %tmp1 = load <8 x i16>* %A 113 %tmp2 = call <8 x i16> @llvm.arm.neon.vqabs.v8i16(<8 x i16> %tmp1) 114 ret <8 x i16> %tmp2 115 } 116 117 define <4 x i32> @vqabsQs32(<4 x i32>* %A) nounwind { 118 ;CHECK: vqabsQs32: 119 ;CHECK: vqabs.s32 120 %tmp1 = load <4 x i32>* %A 121 %tmp2 = call <4 x i32> @llvm.arm.neon.vqabs.v4i32(<4 x i32> %tmp1) 122 ret <4 x i32> %tmp2 123 } 124 125 declare <8 x i8> @llvm.arm.neon.vqabs.v8i8(<8 x i8>) nounwind readnone 126 declare <4 x i16> @llvm.arm.neon.vqabs.v4i16(<4 x i16>) nounwind readnone 127 declare <2 x i32> @llvm.arm.neon.vqabs.v2i32(<2 x i32>) nounwind readnone 128 129 declare <16 x i8> @llvm.arm.neon.vqabs.v16i8(<16 x i8>) nounwind readnone 130 declare <8 x i16> @llvm.arm.neon.vqabs.v8i16(<8 x i16>) nounwind readnone 131 declare <4 x i32> @llvm.arm.neon.vqabs.v4i32(<4 x i32>) nounwind readnone 132
