1 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s 2 3 define <8 x i8> @test_vextd(<8 x i8>* %A, <8 x i8>* %B) nounwind { 4 ;CHECK: test_vextd: 5 ;CHECK: vext 6 %tmp1 = load <8 x i8>* %A 7 %tmp2 = load <8 x i8>* %B 8 %tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10> 9 ret <8 x i8> %tmp3 10 } 11 12 define <8 x i8> @test_vextRd(<8 x i8>* %A, <8 x i8>* %B) nounwind { 13 ;CHECK: test_vextRd: 14 ;CHECK: vext 15 %tmp1 = load <8 x i8>* %A 16 %tmp2 = load <8 x i8>* %B 17 %tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 13, i32 14, i32 15, i32 0, i32 1, i32 2, i32 3, i32 4> 18 ret <8 x i8> %tmp3 19 } 20 21 define <16 x i8> @test_vextq(<16 x i8>* %A, <16 x i8>* %B) nounwind { 22 ;CHECK: test_vextq: 23 ;CHECK: vext 24 %tmp1 = load <16 x i8>* %A 25 %tmp2 = load <16 x i8>* %B 26 %tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18> 27 ret <16 x i8> %tmp3 28 } 29 30 define <16 x i8> @test_vextRq(<16 x i8>* %A, <16 x i8>* %B) nounwind { 31 ;CHECK: test_vextRq: 32 ;CHECK: vext 33 %tmp1 = load <16 x i8>* %A 34 %tmp2 = load <16 x i8>* %B 35 %tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6> 36 ret <16 x i8> %tmp3 37 } 38 39 define <4 x i16> @test_vextd16(<4 x i16>* %A, <4 x i16>* %B) nounwind { 40 ;CHECK: test_vextd16: 41 ;CHECK: vext 42 %tmp1 = load <4 x i16>* %A 43 %tmp2 = load <4 x i16>* %B 44 %tmp3 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i32> <i32 3, i32 4, i32 5, i32 6> 45 ret <4 x i16> %tmp3 46 } 47 48 define <4 x i32> @test_vextq32(<4 x i32>* %A, <4 x i32>* %B) nounwind { 49 ;CHECK: test_vextq32: 50 ;CHECK: vext 51 %tmp1 = load <4 x i32>* %A 52 %tmp2 = load <4 x i32>* %B 53 %tmp3 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> <i32 3, i32 4, i32 5, i32 6> 54 ret <4 x i32> %tmp3 55 } 56 57 ; Undef shuffle indices should not prevent matching to VEXT: 58 59 define <8 x i8> @test_vextd_undef(<8 x i8>* %A, <8 x i8>* %B) nounwind { 60 ;CHECK: test_vextd_undef: 61 ;CHECK: vext 62 %tmp1 = load <8 x i8>* %A 63 %tmp2 = load <8 x i8>* %B 64 %tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 3, i32 undef, i32 undef, i32 6, i32 7, i32 8, i32 9, i32 10> 65 ret <8 x i8> %tmp3 66 } 67 68 define <16 x i8> @test_vextRq_undef(<16 x i8>* %A, <16 x i8>* %B) nounwind { 69 ;CHECK: test_vextRq_undef: 70 ;CHECK: vext 71 %tmp1 = load <16 x i8>* %A 72 %tmp2 = load <16 x i8>* %B 73 %tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 23, i32 24, i32 25, i32 26, i32 undef, i32 undef, i32 29, i32 30, i32 31, i32 0, i32 1, i32 2, i32 3, i32 4, i32 undef, i32 6> 74 ret <16 x i8> %tmp3 75 } 76 77 ; Tests for ReconstructShuffle function. Indices have to be carefully 78 ; chosen to reach lowering phase as a BUILD_VECTOR. 79 80 ; One vector needs vext, the other can be handled by extract_subvector 81 ; Also checks interleaving of sources is handled correctly. 82 ; Essence: a vext is used on %A and something saner than stack load/store for final result. 83 define <4 x i16> @test_interleaved(<8 x i16>* %A, <8 x i16>* %B) nounwind { 84 ;CHECK: test_interleaved: 85 ;CHECK: vext.16 86 ;CHECK-NOT: vext.16 87 ;CHECK: vzip.16 88 %tmp1 = load <8 x i16>* %A 89 %tmp2 = load <8 x i16>* %B 90 %tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <4 x i32> <i32 3, i32 8, i32 5, i32 9> 91 ret <4 x i16> %tmp3 92 } 93 94 ; An undef in the shuffle list should still be optimizable 95 define <4 x i16> @test_undef(<8 x i16>* %A, <8 x i16>* %B) nounwind { 96 ;CHECK: test_undef: 97 ;CHECK: vzip.16 98 %tmp1 = load <8 x i16>* %A 99 %tmp2 = load <8 x i16>* %B 100 %tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <4 x i32> <i32 undef, i32 8, i32 5, i32 9> 101 ret <4 x i16> %tmp3 102 } 103 104 ; We should ignore a build_vector with more than two sources. 105 ; Use illegal <32 x i16> type to produce such a shuffle after legalizing types. 106 ; Try to look for fallback to stack expansion. 107 define <4 x i16> @test_multisource(<32 x i16>* %B) nounwind { 108 ;CHECK: test_multisource: 109 ;CHECK: vst1.16 110 %tmp1 = load <32 x i16>* %B 111 %tmp2 = shufflevector <32 x i16> %tmp1, <32 x i16> undef, <4 x i32> <i32 0, i32 8, i32 16, i32 24> 112 ret <4 x i16> %tmp2 113 } 114 115 ; We don't handle shuffles using more than half of a 128-bit vector. 116 ; Again, test for fallback to stack expansion 117 define <4 x i16> @test_largespan(<8 x i16>* %B) nounwind { 118 ;CHECK: test_largespan: 119 ;CHECK: vst1.16 120 %tmp1 = load <8 x i16>* %B 121 %tmp2 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6> 122 ret <4 x i16> %tmp2 123 } 124 125 ; The actual shuffle code only handles some cases, make sure we check 126 ; this rather than blindly emitting a VECTOR_SHUFFLE (infinite 127 ; lowering loop can result otherwise). 128 define <8 x i16> @test_illegal(<8 x i16>* %A, <8 x i16>* %B) nounwind { 129 ;CHECK: test_illegal: 130 ;CHECK: vst1.16 131 %tmp1 = load <8 x i16>* %A 132 %tmp2 = load <8 x i16>* %B 133 %tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 0, i32 7, i32 5, i32 13, i32 3, i32 2, i32 2, i32 9> 134 ret <8 x i16> %tmp3 135 } 136
