1 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s 2 3 define <8 x i16> @vshlls8(<8 x i8>* %A) nounwind { 4 ;CHECK: vshlls8: 5 ;CHECK: vshll.s8 6 %tmp1 = load <8 x i8>* %A 7 %tmp2 = call <8 x i16> @llvm.arm.neon.vshiftls.v8i16(<8 x i8> %tmp1, <8 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >) 8 ret <8 x i16> %tmp2 9 } 10 11 define <4 x i32> @vshlls16(<4 x i16>* %A) nounwind { 12 ;CHECK: vshlls16: 13 ;CHECK: vshll.s16 14 %tmp1 = load <4 x i16>* %A 15 %tmp2 = call <4 x i32> @llvm.arm.neon.vshiftls.v4i32(<4 x i16> %tmp1, <4 x i16> < i16 15, i16 15, i16 15, i16 15 >) 16 ret <4 x i32> %tmp2 17 } 18 19 define <2 x i64> @vshlls32(<2 x i32>* %A) nounwind { 20 ;CHECK: vshlls32: 21 ;CHECK: vshll.s32 22 %tmp1 = load <2 x i32>* %A 23 %tmp2 = call <2 x i64> @llvm.arm.neon.vshiftls.v2i64(<2 x i32> %tmp1, <2 x i32> < i32 31, i32 31 >) 24 ret <2 x i64> %tmp2 25 } 26 27 define <8 x i16> @vshllu8(<8 x i8>* %A) nounwind { 28 ;CHECK: vshllu8: 29 ;CHECK: vshll.u8 30 %tmp1 = load <8 x i8>* %A 31 %tmp2 = call <8 x i16> @llvm.arm.neon.vshiftlu.v8i16(<8 x i8> %tmp1, <8 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >) 32 ret <8 x i16> %tmp2 33 } 34 35 define <4 x i32> @vshllu16(<4 x i16>* %A) nounwind { 36 ;CHECK: vshllu16: 37 ;CHECK: vshll.u16 38 %tmp1 = load <4 x i16>* %A 39 %tmp2 = call <4 x i32> @llvm.arm.neon.vshiftlu.v4i32(<4 x i16> %tmp1, <4 x i16> < i16 15, i16 15, i16 15, i16 15 >) 40 ret <4 x i32> %tmp2 41 } 42 43 define <2 x i64> @vshllu32(<2 x i32>* %A) nounwind { 44 ;CHECK: vshllu32: 45 ;CHECK: vshll.u32 46 %tmp1 = load <2 x i32>* %A 47 %tmp2 = call <2 x i64> @llvm.arm.neon.vshiftlu.v2i64(<2 x i32> %tmp1, <2 x i32> < i32 31, i32 31 >) 48 ret <2 x i64> %tmp2 49 } 50 51 ; The following tests use the maximum shift count, so the signedness is 52 ; irrelevant. Test both signed and unsigned versions. 53 define <8 x i16> @vshlli8(<8 x i8>* %A) nounwind { 54 ;CHECK: vshlli8: 55 ;CHECK: vshll.i8 56 %tmp1 = load <8 x i8>* %A 57 %tmp2 = call <8 x i16> @llvm.arm.neon.vshiftls.v8i16(<8 x i8> %tmp1, <8 x i8> < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >) 58 ret <8 x i16> %tmp2 59 } 60 61 define <4 x i32> @vshlli16(<4 x i16>* %A) nounwind { 62 ;CHECK: vshlli16: 63 ;CHECK: vshll.i16 64 %tmp1 = load <4 x i16>* %A 65 %tmp2 = call <4 x i32> @llvm.arm.neon.vshiftlu.v4i32(<4 x i16> %tmp1, <4 x i16> < i16 16, i16 16, i16 16, i16 16 >) 66 ret <4 x i32> %tmp2 67 } 68 69 define <2 x i64> @vshlli32(<2 x i32>* %A) nounwind { 70 ;CHECK: vshlli32: 71 ;CHECK: vshll.i32 72 %tmp1 = load <2 x i32>* %A 73 %tmp2 = call <2 x i64> @llvm.arm.neon.vshiftls.v2i64(<2 x i32> %tmp1, <2 x i32> < i32 32, i32 32 >) 74 ret <2 x i64> %tmp2 75 } 76 77 declare <8 x i16> @llvm.arm.neon.vshiftls.v8i16(<8 x i8>, <8 x i8>) nounwind readnone 78 declare <4 x i32> @llvm.arm.neon.vshiftls.v4i32(<4 x i16>, <4 x i16>) nounwind readnone 79 declare <2 x i64> @llvm.arm.neon.vshiftls.v2i64(<2 x i32>, <2 x i32>) nounwind readnone 80 81 declare <8 x i16> @llvm.arm.neon.vshiftlu.v8i16(<8 x i8>, <8 x i8>) nounwind readnone 82 declare <4 x i32> @llvm.arm.neon.vshiftlu.v4i32(<4 x i16>, <4 x i16>) nounwind readnone 83 declare <2 x i64> @llvm.arm.neon.vshiftlu.v2i64(<2 x i32>, <2 x i32>) nounwind readnone 84
