1 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s 2 3 define <8 x i8> @vshrns8(<8 x i16>* %A) nounwind { 4 ;CHECK: vshrns8: 5 ;CHECK: vshrn.i16 6 %tmp1 = load <8 x i16>* %A 7 %tmp2 = call <8 x i8> @llvm.arm.neon.vshiftn.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >) 8 ret <8 x i8> %tmp2 9 } 10 11 define <4 x i16> @vshrns16(<4 x i32>* %A) nounwind { 12 ;CHECK: vshrns16: 13 ;CHECK: vshrn.i32 14 %tmp1 = load <4 x i32>* %A 15 %tmp2 = call <4 x i16> @llvm.arm.neon.vshiftn.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >) 16 ret <4 x i16> %tmp2 17 } 18 19 define <2 x i32> @vshrns32(<2 x i64>* %A) nounwind { 20 ;CHECK: vshrns32: 21 ;CHECK: vshrn.i64 22 %tmp1 = load <2 x i64>* %A 23 %tmp2 = call <2 x i32> @llvm.arm.neon.vshiftn.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >) 24 ret <2 x i32> %tmp2 25 } 26 27 declare <8 x i8> @llvm.arm.neon.vshiftn.v8i8(<8 x i16>, <8 x i16>) nounwind readnone 28 declare <4 x i16> @llvm.arm.neon.vshiftn.v4i16(<4 x i32>, <4 x i32>) nounwind readnone 29 declare <2 x i32> @llvm.arm.neon.vshiftn.v2i32(<2 x i64>, <2 x i64>) nounwind readnone 30 31 define <8 x i8> @vrshrns8(<8 x i16>* %A) nounwind { 32 ;CHECK: vrshrns8: 33 ;CHECK: vrshrn.i16 34 %tmp1 = load <8 x i16>* %A 35 %tmp2 = call <8 x i8> @llvm.arm.neon.vrshiftn.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >) 36 ret <8 x i8> %tmp2 37 } 38 39 define <4 x i16> @vrshrns16(<4 x i32>* %A) nounwind { 40 ;CHECK: vrshrns16: 41 ;CHECK: vrshrn.i32 42 %tmp1 = load <4 x i32>* %A 43 %tmp2 = call <4 x i16> @llvm.arm.neon.vrshiftn.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >) 44 ret <4 x i16> %tmp2 45 } 46 47 define <2 x i32> @vrshrns32(<2 x i64>* %A) nounwind { 48 ;CHECK: vrshrns32: 49 ;CHECK: vrshrn.i64 50 %tmp1 = load <2 x i64>* %A 51 %tmp2 = call <2 x i32> @llvm.arm.neon.vrshiftn.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >) 52 ret <2 x i32> %tmp2 53 } 54 55 declare <8 x i8> @llvm.arm.neon.vrshiftn.v8i8(<8 x i16>, <8 x i16>) nounwind readnone 56 declare <4 x i16> @llvm.arm.neon.vrshiftn.v4i16(<4 x i32>, <4 x i32>) nounwind readnone 57 declare <2 x i32> @llvm.arm.neon.vrshiftn.v2i32(<2 x i64>, <2 x i64>) nounwind readnone 58
