1 ; Ensure that the select instruction is supported and is lowered to 2 ; some sort of branch instruction. 3 ; 4 ; RUN: llc < %s -march=mblaze -mattr=+mul,+fpu,+barrel | FileCheck %s 5 6 declare i32 @printf(i8*, ...) 7 @MSG = internal constant [13 x i8] c"Message: %d\0A\00" 8 9 @BLKS = private constant [5 x i8*] 10 [ i8* blockaddress(@brind, %L1), 11 i8* blockaddress(@brind, %L2), 12 i8* blockaddress(@brind, %L3), 13 i8* blockaddress(@brind, %L4), 14 i8* blockaddress(@brind, %L5) ] 15 16 define i32 @brind(i32 %a, i32 %b) 17 { 18 ; CHECK: brind: 19 entry: 20 br label %loop 21 22 loop: 23 %tmp.0 = phi i32 [ 0, %entry ], [ %tmp.8, %finish ] 24 %dst.0 = getelementptr [5 x i8*]* @BLKS, i32 0, i32 %tmp.0 25 %dst.1 = load i8** %dst.0 26 indirectbr i8* %dst.1, [ label %L1, 27 label %L2, 28 label %L3, 29 label %L4, 30 label %L5 ] 31 ; CHECK: brad {{r[0-9]*}} 32 33 L1: 34 %tmp.1 = add i32 %a, %b 35 br label %finish 36 ; CHECK: brid 37 38 L2: 39 %tmp.2 = sub i32 %a, %b 40 br label %finish 41 ; CHECK: brid 42 43 L3: 44 %tmp.3 = mul i32 %a, %b 45 br label %finish 46 ; CHECK: brid 47 48 L4: 49 %tmp.4 = sdiv i32 %a, %b 50 br label %finish 51 ; CHECK: brid 52 53 L5: 54 %tmp.5 = srem i32 %a, %b 55 br label %finish 56 57 finish: 58 %tmp.6 = phi i32 [ %tmp.1, %L1 ], 59 [ %tmp.2, %L2 ], 60 [ %tmp.3, %L3 ], 61 [ %tmp.4, %L4 ], 62 [ %tmp.5, %L5 ] 63 64 call i32 (i8*,...)* @printf( i8* getelementptr([13 x i8]* @MSG,i32 0,i32 0), 65 i32 %tmp.6) 66 67 %tmp.7 = add i32 %tmp.0, 1 68 %tmp.8 = urem i32 %tmp.7, 5 69 70 br label %loop 71 ; CHECK: brad {{r[0-9]*}} 72 } 73
