1 ; RUN: llc -march=msp430 < %s | FileCheck %s 2 target datalayout = "e-p:16:16:16-i1:8:8-i8:8:8-i16:16:16-i32:16:32" 3 target triple = "msp430-generic-generic" 4 5 define i16 @sccweqand(i16 %a, i16 %b) nounwind { 6 %t1 = and i16 %a, %b 7 %t2 = icmp eq i16 %t1, 0 8 %t3 = zext i1 %t2 to i16 9 ret i16 %t3 10 } 11 ; CHECK: sccweqand: 12 ; CHECK: bit.w r14, r15 13 ; CHECK: mov.w r2, r15 14 ; CHECK: rra.w r15 15 ; CHECK: and.w #1, r15 16 17 define i16 @sccwneand(i16 %a, i16 %b) nounwind { 18 %t1 = and i16 %a, %b 19 %t2 = icmp ne i16 %t1, 0 20 %t3 = zext i1 %t2 to i16 21 ret i16 %t3 22 } 23 ; CHECK: sccwneand: 24 ; CHECK: bit.w r14, r15 25 ; CHECK: mov.w r2, r15 26 ; CHECK: and.w #1, r15 27 28 define i16 @sccwne(i16 %a, i16 %b) nounwind { 29 %t1 = icmp ne i16 %a, %b 30 %t2 = zext i1 %t1 to i16 31 ret i16 %t2 32 } 33 ; CHECK:sccwne: 34 ; CHECK: cmp.w r14, r15 35 ; CHECK: mov.w r2, r15 36 ; CHECK: rra.w r15 37 ; CHECK: and.w #1, r15 38 ; CHECK: xor.w #1, r15 39 40 define i16 @sccweq(i16 %a, i16 %b) nounwind { 41 %t1 = icmp eq i16 %a, %b 42 %t2 = zext i1 %t1 to i16 43 ret i16 %t2 44 } 45 ; CHECK:sccweq: 46 ; CHECK: cmp.w r14, r15 47 ; CHECK: mov.w r2, r15 48 ; CHECK: rra.w r15 49 ; CHECK: and.w #1, r15 50 51 define i16 @sccwugt(i16 %a, i16 %b) nounwind { 52 %t1 = icmp ugt i16 %a, %b 53 %t2 = zext i1 %t1 to i16 54 ret i16 %t2 55 } 56 ; CHECK:sccwugt: 57 ; CHECK: cmp.w r15, r14 58 ; CHECK: mov.w r2, r15 59 ; CHECK: and.w #1, r15 60 ; CHECK: xor.w #1, r15 61 62 define i16 @sccwuge(i16 %a, i16 %b) nounwind { 63 %t1 = icmp uge i16 %a, %b 64 %t2 = zext i1 %t1 to i16 65 ret i16 %t2 66 } 67 ; CHECK:sccwuge: 68 ; CHECK: cmp.w r14, r15 69 ; CHECK: mov.w r2, r15 70 ; CHECK: and.w #1, r15 71 72 define i16 @sccwult(i16 %a, i16 %b) nounwind { 73 %t1 = icmp ult i16 %a, %b 74 %t2 = zext i1 %t1 to i16 75 ret i16 %t2 76 } 77 ; CHECK:sccwult: 78 ; CHECK: cmp.w r14, r15 79 ; CHECK: mov.w r2, r15 80 ; CHECK: and.w #1, r15 81 ; CHECK: xor.w #1, r15 82 83 define i16 @sccwule(i16 %a, i16 %b) nounwind { 84 %t1 = icmp ule i16 %a, %b 85 %t2 = zext i1 %t1 to i16 86 ret i16 %t2 87 } 88 ; CHECK:sccwule: 89 ; CHECK: cmp.w r15, r14 90 ; CHECK: mov.w r2, r15 91 ; CHECK: and.w #1, r15 92 93 define i16 @sccwsgt(i16 %a, i16 %b) nounwind { 94 %t1 = icmp sgt i16 %a, %b 95 %t2 = zext i1 %t1 to i16 96 ret i16 %t2 97 } 98 99 define i16 @sccwsge(i16 %a, i16 %b) nounwind { 100 %t1 = icmp sge i16 %a, %b 101 %t2 = zext i1 %t1 to i16 102 ret i16 %t2 103 } 104 105 define i16 @sccwslt(i16 %a, i16 %b) nounwind { 106 %t1 = icmp slt i16 %a, %b 107 %t2 = zext i1 %t1 to i16 108 ret i16 %t2 109 } 110 111 define i16 @sccwsle(i16 %a, i16 %b) nounwind { 112 %t1 = icmp sle i16 %a, %b 113 %t2 = zext i1 %t1 to i16 114 ret i16 %t2 115 } 116 117
