1 ; RUN: llc < %s -march=x86 -mattr=+sse42 | FileCheck %s 2 3 ; widening shuffle v3float and then a add 4 define void @shuf(<3 x float>* %dst.addr, <3 x float> %src1,<3 x float> %src2) nounwind { 5 entry: 6 ; CHECK: shuf: 7 ; CHECK: extractps 8 ; CHECK: extractps 9 %x = shufflevector <3 x float> %src1, <3 x float> %src2, <3 x i32> < i32 0, i32 1, i32 2> 10 %val = fadd <3 x float> %x, %src2 11 store <3 x float> %val, <3 x float>* %dst.addr 12 ret void 13 } 14 15 16 ; widening shuffle v3float with a different mask and then a add 17 define void @shuf2(<3 x float>* %dst.addr, <3 x float> %src1,<3 x float> %src2) nounwind { 18 entry: 19 ; CHECK: shuf2: 20 ; CHECK: extractps 21 ; CHECK: extractps 22 %x = shufflevector <3 x float> %src1, <3 x float> %src2, <3 x i32> < i32 0, i32 4, i32 2> 23 %val = fadd <3 x float> %x, %src2 24 store <3 x float> %val, <3 x float>* %dst.addr 25 ret void 26 } 27 28 ; Example of when widening a v3float operation causes the DAG to replace a node 29 ; with the operation that we are currently widening, i.e. when replacing 30 ; opA with opB, the DAG will produce new operations with opA. 31 define void @shuf3(<4 x float> %tmp10, <4 x float> %vecinit15, <4 x float>* %dst) nounwind { 32 entry: 33 ; CHECK: pshufd 34 %shuffle.i.i.i12 = shufflevector <4 x float> %tmp10, <4 x float> %vecinit15, <4 x i32> <i32 0, i32 1, i32 4, i32 5> 35 %tmp25.i.i = shufflevector <4 x float> %shuffle.i.i.i12, <4 x float> undef, <3 x i32> <i32 0, i32 1, i32 2> 36 %tmp1.i.i = shufflevector <3 x float> %tmp25.i.i, <3 x float> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 3> 37 %tmp3.i13 = shufflevector <4 x float> %tmp1.i.i, <4 x float> undef, <3 x i32> <i32 0, i32 1, i32 2> ; <<3 x float>> 38 %tmp6.i14 = shufflevector <3 x float> %tmp3.i13, <3 x float> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 3> 39 %tmp97.i = shufflevector <4 x float> %tmp6.i14, <4 x float> undef, <3 x i32> <i32 0, i32 1, i32 2> 40 %tmp2.i18 = shufflevector <3 x float> %tmp97.i, <3 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 2> 41 %t5 = bitcast <4 x float> %tmp2.i18 to <4 x i32> 42 %shr.i.i19 = lshr <4 x i32> %t5, <i32 19, i32 19, i32 19, i32 19> 43 %and.i.i20 = and <4 x i32> %shr.i.i19, <i32 4080, i32 4080, i32 4080, i32 4080> 44 %shuffle.i.i.i21 = shufflevector <4 x float> %tmp2.i18, <4 x float> undef, <4 x i32> <i32 2, i32 3, i32 2, i32 3> 45 store <4 x float> %shuffle.i.i.i21, <4 x float>* %dst 46 ret void 47 } 48 49
