1 ; RUN: opt < %s -indvars 2 ; PR4052 3 ; PR4054 4 5 ; Don't treat an and with 0 as a mask (trunc+zext). 6 7 define i32 @int80(i8 signext %p_71) nounwind { 8 entry: 9 br label %bb 10 11 bb: ; preds = %bb6, %entry 12 %p_71_addr.0 = phi i8 [ %p_71, %entry ], [ %0, %bb6 ] ; <i8> [#uses=0] 13 br i1 undef, label %bb4, label %bb1 14 15 bb1: ; preds = %bb 16 ret i32 0 17 18 bb4: ; preds = %bb4, %bb 19 br i1 undef, label %bb6, label %bb4 20 21 bb6: ; preds = %bb4 22 %0 = and i8 0, 0 ; <i8> [#uses=1] 23 br label %bb 24 } 25 26 @x = common global i32 0 ; <i32*> [#uses=1] 27 28 define signext i8 @safe_sub_func_int32_t_s_s(i32 %_si1, i8 signext %_si2) nounwind { 29 entry: 30 %_si1_addr = alloca i32 ; <i32*> [#uses=3] 31 %_si2_addr = alloca i8 ; <i8*> [#uses=3] 32 %retval = alloca i32 ; <i32*> [#uses=2] 33 %0 = alloca i32 ; <i32*> [#uses=2] 34 %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0] 35 store i32 %_si1, i32* %_si1_addr 36 store i8 %_si2, i8* %_si2_addr 37 %1 = load i8* %_si2_addr, align 1 ; <i8> [#uses=1] 38 %2 = sext i8 %1 to i32 ; <i32> [#uses=1] 39 %3 = load i32* %_si1_addr, align 4 ; <i32> [#uses=1] 40 %4 = xor i32 %2, %3 ; <i32> [#uses=1] 41 %5 = load i8* %_si2_addr, align 1 ; <i8> [#uses=1] 42 %6 = sext i8 %5 to i32 ; <i32> [#uses=1] 43 %7 = sub i32 7, %6 ; <i32> [#uses=1] 44 %8 = load i32* %_si1_addr, align 4 ; <i32> [#uses=1] 45 %9 = shl i32 %8, %7 ; <i32> [#uses=1] 46 %10 = and i32 %4, %9 ; <i32> [#uses=1] 47 %11 = icmp slt i32 %10, 0 ; <i1> [#uses=1] 48 %12 = zext i1 %11 to i32 ; <i32> [#uses=1] 49 store i32 %12, i32* %0, align 4 50 %13 = load i32* %0, align 4 ; <i32> [#uses=1] 51 store i32 %13, i32* %retval, align 4 52 br label %return 53 54 return: ; preds = %entry 55 %retval1 = load i32* %retval ; <i32> [#uses=1] 56 %retval12 = trunc i32 %retval1 to i8 ; <i8> [#uses=1] 57 ret i8 %retval12 58 } 59 60 define i32 @safe_sub_func_uint64_t_u_u(i32 %_ui1, i32 %_ui2) nounwind { 61 entry: 62 %_ui1_addr = alloca i32 ; <i32*> [#uses=2] 63 %_ui2_addr = alloca i32 ; <i32*> [#uses=1] 64 %retval = alloca i32 ; <i32*> [#uses=2] 65 %0 = alloca i32 ; <i32*> [#uses=2] 66 %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0] 67 store i32 %_ui1, i32* %_ui1_addr 68 store i32 %_ui2, i32* %_ui2_addr 69 %1 = load i32* %_ui1_addr, align 4 ; <i32> [#uses=1] 70 %2 = sub i32 %1, 1 ; <i32> [#uses=1] 71 store i32 %2, i32* %0, align 4 72 %3 = load i32* %0, align 4 ; <i32> [#uses=1] 73 store i32 %3, i32* %retval, align 4 74 br label %return 75 76 return: ; preds = %entry 77 %retval1 = load i32* %retval ; <i32> [#uses=1] 78 ret i32 %retval1 79 } 80 81 define void @int87(i8 signext %p_48, i8 signext %p_49) nounwind { 82 entry: 83 %p_48_addr = alloca i8 ; <i8*> [#uses=1] 84 %p_49_addr = alloca i8 ; <i8*> [#uses=1] 85 %l_52 = alloca i32 ; <i32*> [#uses=7] 86 %vol.0 = alloca i32 ; <i32*> [#uses=1] 87 %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0] 88 store i8 %p_48, i8* %p_48_addr 89 store i8 %p_49, i8* %p_49_addr 90 br label %bb4 91 92 bb: ; preds = %bb4 93 %0 = volatile load i32* @x, align 4 ; <i32> [#uses=1] 94 store i32 %0, i32* %vol.0, align 4 95 store i32 0, i32* %l_52, align 4 96 br label %bb2 97 98 bb1: ; preds = %bb2 99 %1 = load i32* %l_52, align 4 ; <i32> [#uses=1] 100 %2 = call i32 @safe_sub_func_uint64_t_u_u(i32 %1, i32 1) nounwind ; <i32> [#uses=1] 101 store i32 %2, i32* %l_52, align 4 102 br label %bb2 103 104 bb2: ; preds = %bb1, %bb 105 %3 = load i32* %l_52, align 4 ; <i32> [#uses=1] 106 %4 = icmp eq i32 %3, 0 ; <i1> [#uses=1] 107 br i1 %4, label %bb1, label %bb3 108 109 bb3: ; preds = %bb2 110 %5 = load i32* %l_52, align 4 ; <i32> [#uses=1] 111 %6 = call signext i8 @safe_sub_func_int32_t_s_s(i32 %5, i8 signext 1) nounwind ; <i8> [#uses=1] 112 %7 = sext i8 %6 to i32 ; <i32> [#uses=1] 113 store i32 %7, i32* %l_52, align 4 114 br label %bb4 115 116 bb4: ; preds = %bb3, %entry 117 %8 = load i32* %l_52, align 4 ; <i32> [#uses=1] 118 %9 = icmp ne i32 %8, 0 ; <i1> [#uses=1] 119 br i1 %9, label %bb, label %bb5 120 121 bb5: ; preds = %bb4 122 br label %return 123 124 return: ; preds = %bb5 125 ret void 126 } 127
