Lines Matching defs:t5
11013 // op t5, t6 <- out1, out2, [bitinstr.val]
11014 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val])
11015 // mov ECX, EBX <- t5, t6
11113 unsigned t5 = F->getRegInfo().createVirtualRegister(RC);
11116 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5);
11118 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5);
11140 MIB.addReg(t5);
