Lines Matching full:i64
180 static MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
231 addRegisterClass(MVT::i64, X86::GR64RegisterClass);
236 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
237 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
238 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
259 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand);
263 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
291 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
292 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
315 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
325 // With SSE3 we can use fisttpll to convert to a signed i64; without
336 // Without SSE, i64->f64 goes through memory.
337 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
389 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
399 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
409 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
412 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
431 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
432 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
442 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
446 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
447 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
448 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
449 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
450 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
457 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
458 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
459 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
484 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom);
485 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
486 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
487 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
488 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
489 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
490 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
491 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
505 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
506 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
517 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
540 MVT::i64 : MVT::i32, Custom);
543 MVT::i64 : MVT::i32, Custom);
546 MVT::i64 : MVT::i32, Expand);
567 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
1273 return MVT::i64;
1336 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1459 i64, ValToCopy);
1764 else if (Is64Bit && RegVT == MVT::i64)
1822 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1890 // Fixup to set vararg frame on shadow area (4 x i64).
1914 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2025 EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
2135 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
3609 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
5034 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, 2, MVT::i64,
5055 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
5104 // If this is an insertion of an i64 value on x86-32, and if the top bits of
5109 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
5147 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
5895 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
5896 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
6974 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
7118 Op.getOperand(0).getValueType() == MVT::i64)
7594 i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
7601 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
7828 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
7834 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
7845 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
7849 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
7853 // For i64 source, we need to add the appropriate power of 2 if the input
7865 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
7867 MVT::i64, MMO);
7872 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
7873 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
7906 DstTy = MVT::i64;
7909 assert(DstTy.getSimpleVT() <= MVT::i64 &&
7918 DstTy == MVT::i64 &&
7936 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
7943 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
8940 EVT SPTy = Is64Bit ? MVT::i64 : MVT::i32;
8959 getRegClassFor(Subtarget->is64Bit() ? MVT::i64:MVT::i32);
9095 MVT::i64,
9430 Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
9523 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9524 DAG.getConstant(2, MVT::i64));
9532 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9533 DAG.getConstant(10, MVT::i64));
9538 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9539 DAG.getConstant(12, MVT::i64));
9546 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9547 DAG.getConstant(20, MVT::i64));
9553 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9554 DAG.getConstant(22, MVT::i64));
10089 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
10253 case MVT::i64:
10281 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
10282 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
10284 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
10287 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
10299 assert((DstVT == MVT::i64 ||
10302 // i64 <=> MMX conversions are Legal.
10303 if (SrcVT==MVT::i64 && DstVT.isVector())
10305 if (DstVT==MVT::i64 && SrcVT.isVector())
10481 assert (Node->getValueType(0) == MVT::i64 &&
10482 "Only know how to expand i64 atomics");
10493 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64,
10496 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
10539 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2));
10545 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
10547 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
10840 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
11387 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
11394 // i64 overflow_area (address)
11395 // i64 reg_save_area (address)
11782 getRegClassFor(Is64Bit ? MVT::i64:MVT::i32);
12805 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
12806 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
12925 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
12926 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
12982 if (VT != MVT::i64)
13303 if (Subtarget->hasBMI() && (VT == MVT::i32 || VT == MVT::i64)) {
13355 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64 && VT != MVT::v2i64)
13699 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
13708 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
13736 // If this is not the MMX case, i.e. we are just turning i64 load/store
13748 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
14055 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
14056 // a 32-bit target where SSE doesn't support i64->FP operations.
14428 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
14671 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
14696 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
14774 else if (VT == MVT::i64 || VT == MVT::f64)
14786 else if (VT == MVT::i64)
14830 case MVT::i64:
14930 } else if (VT == MVT::i64) {
