Home | History | Annotate | Download | only in X86

Lines Matching refs:Extract

91   // Extract from UNDEF is UNDEF.
98 // Extract the relevant 128 bits. Generate an EXTRACT_SUBVECTOR
1059 // Extract subvector is special because the value type
4003 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
4110 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4114 llvm_unreachable("Illegal extract subvector for VEXTRACTF128");
4464 // Extract the 128-bit part containing the splat element and update
5664 // before falling through to the insert/extract cleanup.
5791 // using a single extract together, load it and store it.
5800 // If Elt1 is defined, extract it from the appropriate source. If the
5814 // If Elt0 is defined, extract it from the appropriate source. If the
5951 // source vectors, extract each used 128-bit lane and shuffle them using
5959 // Extract the reference for each half
5979 // Extract the subvectors
6190 /// a vector extract, and if both can be later optimized into a single load.
6226 // Select the input vector, guarding against out of range extract vector.
6859 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
6861 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
6874 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
6876 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
6894 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6898 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
6917 // If this is a 256-bit vector result, first extract the 128-bit vector and
6918 // then extract the element from the 128-bit vector.
6956 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
6958 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
7029 // bits. For example (insert (extract, 3), 2) could be matched by putting
7056 // If this is a 256-bit vector result, first extract the 128-bit vector,
8436 // Extract the LHS vectors
8441 // Extract the RHS vectors
9790 // Extract the LHS vectors
9795 // Extract the RHS vectors
9888 // Extract the two vectors
12521 /// to a simple store and scalar loads to extract the elements.
12541 SDNode *Extract = *UI;
12542 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
12545 if (Extract->getValueType(0) != MVT::i32)
12547 if (!Extract->hasOneUse())
12549 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
12550 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
12552 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
12557 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
12559 Uses.push_back(Extract);
12574 // Replace each use (extract) with a load of the appropriate element.
12577 SDNode *Extract = *UI;
12580 SDValue Idx = Extract->getOperand(1);
12590 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
12595 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);