Lines Matching refs:Opcode
2544 unsigned Opcode = Def->getOpcode();
2545 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
2782 static bool isTargetShuffle(unsigned Opcode) {
2783 switch(Opcode) {
4521 unsigned Opcode = V.getOpcode();
4536 if (isTargetShuffle(Opcode)) {
4541 switch(Opcode) {
4652 if (Opcode == ISD::BITCAST) {
7128 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
7146 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
8178 unsigned Opcode = 0;
8201 Opcode = X86ISD::INC;
8208 Opcode = X86ISD::DEC;
8215 Opcode = X86ISD::ADD;
8257 case ISD::SUB: Opcode = X86ISD::SUB; break;
8258 case ISD::OR: Opcode = X86ISD::OR; break;
8259 case ISD::XOR: Opcode = X86ISD::XOR; break;
8260 case ISD::AND: Opcode = X86ISD::AND; break;
8278 if (Opcode == 0)
8288 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
8589 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
9508 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
9509 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
9517 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
9519 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
9531 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
9534 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
9545 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
9548 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
9612 // This is storing the opcode for MOV32ri.
9613 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
9626 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
10575 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
10577 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys,
10616 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
10617 switch (Opcode) {
11690 // true/false values to select between, and a branch opcode to use.
12055 // Get the X86 opcode to use.
12058 default: llvm_unreachable("illegal opcode!");
12623 unsigned Opcode = 0;
12639 Opcode = X86ISD::FMIN;
12647 Opcode = X86ISD::FMIN;
12656 Opcode = X86ISD::FMIN;
12665 Opcode = X86ISD::FMAX;
12677 Opcode = X86ISD::FMAX;
12686 Opcode = X86ISD::FMAX;
12704 Opcode = X86ISD::FMIN;
12711 Opcode = X86ISD::FMIN;
12720 Opcode = X86ISD::FMIN;
12727 Opcode = X86ISD::FMAX;
12739 Opcode = X86ISD::FMAX;
12748 Opcode = X86ISD::FMAX;
12753 if (Opcode)
12754 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
13137 llvm_unreachable("Unknown shift opcode!");
13188 unsigned opcode;
13192 if (Subtarget->hasXMMInt() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
