Lines Matching refs:Shamt
3301 unsigned Shamt = (i%HalfSize)*2;
3303 Mask |= Elt << Shamt;
4723 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4748 ShAmt = NumZeros;
4756 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4781 ShAmt = NumZeros;
4789 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4795 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
4796 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
6628 unsigned ShAmt = 0;
6631 isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
6636 ShAmt *= EltVT.getSizeInBits();
6637 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
6677 ShAmt *= EltVT.getSizeInBits();
6678 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
7551 SDValue ShAmt = Op.getOperand(2);
7558 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
7559 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
7561 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
7562 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
7565 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
9330 SDValue ShAmt = Op.getOperand(2);
9331 if (isa<ConstantSDNode>(ShAmt))
9398 ShOps[0] = ShAmt;
9403 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 4);
9405 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2);
9410 ShAmt = DAG.getNode(ISD::BITCAST, dl, VT, ShAmt);
9413 Op.getOperand(1), ShAmt);
10123 SDValue ShAmt = DAG.getConstant(BitsDiff, MVT::i32);
10144 Node->getOperand(0), ShAmt);
10151 Tmp1, ShAmt);
12786 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
12788 DAG.getConstant(ShAmt, MVT::i8));
12899 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
12901 DAG.getConstant(ShAmt, MVT::i8));
13052 APInt ShAmt = N1C->getAPIntValue();
13053 Mask = Mask.shl(ShAmt);
