| /external/clang/test/CodeGenCXX/ |
| debug-info-byval.cpp | 4 class DAG {
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCHazardRecognizers.h | 27 const ScheduleDAG *DAG;
31 ScoreboardHazardRecognizer(ItinData, DAG_), DAG(DAG_) {}
|
| PPCISelLowering.cpp | 1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
385 // We have target-specific dag combine patterns for the following nodes:
667 SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
710 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef
713 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4)
717 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef
720 return DAG.getTargetConstant(Val, MVT::i32);
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| ScheduleDAGSDNodes.h | 34 /// the DAG and must be handled explicitly by schedulers.
38 SelectionDAG *DAG; // DAG of the current basic block
47 void Run(SelectionDAG *dag, MachineBasicBlock *bb,
77 /// BuildSchedGraph - Build the SUnit graph from the selection dag that we
|
| LegalizeTypes.h | 1 //===-- LegalizeTypes.h - Definition of the DAG Type Legalizer class ------===//
37 SelectionDAG &DAG;
68 return TLI.getTypeAction(*DAG.getContext(), VT);
73 return TLI.getTypeAction(*DAG.getContext(), VT) == TargetLowering::TypeLegal;
119 explicit DAGTypeLegalizer(SelectionDAG &dag)
120 : TLI(dag.getTargetLoweringInfo()), DAG(dag),
127 /// top-down traversal of the dag, legalizing types as it goes. Returns
201 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Op.getValueType(), Op
[all...] |
| LegalizeVectorOps.cpp | 36 SelectionDAG& DAG;
77 VectorLegalizer(SelectionDAG& dag) :
78 DAG(dag), TLI(dag.getTargetLoweringInfo()), Changed(false) {}
88 DAG.AssignTopologicalOrder();
89 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
90 E = prior(DAG.allnodes_end()); I != llvm::next(E); ++I)
94 SDValue OldRoot = DAG.getRoot();
96 DAG.setRoot(LegalizedNodes[OldRoot])
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| SelectionDAGBuilder.h | 1 //===-- SelectionDAGBuilder.h - Selection-DAG building --------------------===//
83 /// CurDebugLoc - current file + line number. Changes as we build the DAG.
294 SelectionDAG &DAG;
328 /// no subsequent DAG nodes should be created.
334 SelectionDAGBuilder(SelectionDAG &dag, FunctionLoweringInfo &funcinfo,
336 : SDNodeOrder(0), TM(dag.getTarget()), TLI(dag.getTargetLoweringInfo()),
337 DAG(dag), FuncInfo(funcinfo), OptLevel(ol),
338 HasTailCall(false), Context(dag.getContext())
[all...] |
| LegalizeDAG.cpp | 52 SelectionDAG &DAG;
78 DAG.TransferDbgValues(From, To);
82 explicit SelectionDAGLegalize(SelectionDAG &DAG);
175 return DAG.getVectorShuffle(NVT, dl, N1, N2, &Mask[0]);
189 return DAG.getVectorShuffle(NVT, dl, N1, N2, &NewMask[0]);
192 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag)
193 : TM(dag.getTarget()), TLI(dag.getTargetLoweringInfo()),
194 DAG(dag) {
[all...] |
| TargetLowering.cpp | [all...] |
| DAGCombiner.cpp | 1 //===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===//
10 // This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run
11 // both before and after the DAG is legalized.
41 STATISTIC(NodesCombined , "Number of dag nodes combined");
59 SelectionDAG &DAG;
69 // AA - Used for DAG load/store alias analysis.
147 /// target-specific DAG combines.
150 // Visitation implementation - Implement dag node combining for different
282 : DAG(D), TLI(D.getTargetLoweringInfo()), Level(Unrestricted)
[all...] |
| SelectionDAGBuilder.cpp | 1 //===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===//
72 // Limit the width of DAG chains. This is important in general to prevent
73 // prevent DAG-based analysis from blowing up. For example, alias analysis and
76 // future analyses are likely to have the same behavior. Limiting DAG width is
88 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL,
97 static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc DL,
102 return getCopyFromPartsVector(DAG, DL, Parts, NumParts, PartVT, ValueVT);
105 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
119 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits);
122 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2)
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| ScoreboardHazardRecognizer.h | 96 const ScheduleDAG *DAG;
109 const ScheduleDAG *DAG,
|
| /external/llvm/utils/TableGen/ |
| CodeGenRegisters.cpp | 99 throw TGError(TheDef->getLoc(), "Invalid dag '" +
302 // SubRegClasses is a list<dag> containing (RC, subregindex, ...) dags.
305 DagInit *DAG = dynamic_cast<DagInit*>(*i);
306 if (!DAG) throw "SubRegClasses must contain DAGs";
307 DefInit *DAGOp = dynamic_cast<DefInit*>(DAG->getOperator());
310 throw "Operator '" + DAG->getOperator()->getAsString() +
313 for (DagInit::const_arg_iterator ai = DAG->arg_begin(), ae = DAG->arg_end();
|
| /external/llvm/lib/Target/XCore/ |
| XCoreISelLowering.cpp | 1 //===-- XCoreISelLowering.cpp - XCore DAG Lowering Implementation ------===//
158 // We have target-specific dag combine patterns for the following nodes:
166 LowerOperation(SDValue Op, SelectionDAG &DAG) const {
169 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
170 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
171 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
172 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
173 case ISD::BR_JT: return LowerBR_JT(Op, DAG);
174 case ISD::LOAD: return LowerLOAD(Op, DAG);
175 case ISD::STORE: return LowerSTORE(Op, DAG);
[all...] |
| /external/llvm/lib/Target/CellSPU/ |
| SPUISelLowering.cpp | 1 //===-- SPUISelLowering.cpp - Cell SPU DAG Lowering Implementation --------===//
53 //! Expand a library call into an actual call DAG node
61 ExpandLibCall(RTLIB::Libcall LC, SDValue Op, SelectionDAG &DAG,
66 SDValue InChain = DAG.getEntryNode();
72 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
79 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
84 Op.getNode()->getValueType(0).getTypeForEVT(*DAG.getContext());
89 Callee, Args, DAG, Op.getDebugLoc());
458 // We have target-specific dag combine patterns for the following nodes:
558 LowerLOAD(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST)
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | 1 //===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===//
11 // selection DAG.
391 static SDValue PerformADDECombine(SDNode *N, SelectionDAG& DAG,
397 if (Subtarget->hasMips32() && SelectMadd(N, &DAG))
403 static SDValue PerformSUBECombine(SDNode *N, SelectionDAG& DAG,
409 if (Subtarget->hasMips32() && SelectMsub(N, &DAG))
415 static SDValue PerformDivRemCombine(SDNode *N, SelectionDAG& DAG,
428 SDValue DivRem = DAG.getNode(opc, dl, MVT::Glue,
430 SDValue InChain = DAG.getEntryNode();
435 SDValue CopyFromLo = DAG.getCopyFromReg(InChain, dl, LO, Ty
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | 1 //===-- ARMISelLowering.cpp - ARM DAG Lowering Implementation -------------===//
11 // selection DAG.
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | 1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
11 // selection DAG.
61 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
67 SelectionDAG &DAG,
72 SelectionDAG &DAG,
75 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
82 SelectionDAG &DAG,
88 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
93 return DAG.getNode(ISD::UNDEF, dl, ResultVT);
107 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32)
[all...] |
