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    Searched defs:MCID (Results 1 - 25 of 46) sorted by null

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  /external/llvm/lib/CodeGen/
ExpandISelPseudos.cpp 65 const MCInstrDesc &MCID = MI->getDesc();
66 if (MCID.usesCustomInsertionHook()) {
ScoreboardHazardRecognizer.cpp 118 const MCInstrDesc *MCID = DAG->getInstrDesc(SU);
119 if (MCID == NULL) {
123 unsigned idx = MCID->getSchedClass();
176 const MCInstrDesc *MCID = DAG->getInstrDesc(SU);
177 assert(MCID && "The scheduler must filter non-machineinstrs");
178 if (DAG->TII->isZeroCost(MCID->Opcode))
185 unsigned idx = MCID->getSchedClass();
PeepholeOptimizer.cpp 355 const MCInstrDesc &MCID = MI->getDesc();
356 if (!MCID.isMoveImmediate())
358 if (MCID.getNumDefs() != 1)
431 const MCInstrDesc &MCID = MI->getDesc();
433 if (MCID.isBitcast()) {
441 } else if (MCID.isCompare()) {
TargetInstrInfoImpl.cpp 62 const MCInstrDesc &MCID = MI->getDesc();
63 bool HasDef = MCID.getNumDefs();
124 const MCInstrDesc &MCID = MI->getDesc();
125 if (!MCID.isCommutable())
129 SrcOpIdx1 = MCID.getNumDefs();
142 const MCInstrDesc &MCID = MI->getDesc();
143 if (!MCID.isPredicable())
147 if (MCID.OpInfo[i].isPredicate()) {
386 const MCInstrDesc &MCID = MI->getDesc();
389 if (MCID.isNotDuplicable() || MCID.mayStore() |
    [all...]
MachineCSE.cpp 263 const MCInstrDesc &MCID = MI->getDesc();
264 if (MCID.mayStore() || MCID.isCall() || MCID.isTerminator() ||
268 if (MCID.mayLoad()) {
ScheduleDAGInstrs.cpp 241 const MCInstrDesc &MCID = MI->getDesc();
242 assert(!MCID.isTerminator() && !MI->isLabel() &&
246 SU->isCall = MCID.isCall();
247 SU->isCommutable = MCID.isCommutable();
422 if (MCID.isCall() || MI->hasUnmodeledSideEffects() ||
424 (!MCID.mayLoad() || !MI->isInvariantLoad(AA)))) {
463 } else if (MCID.mayStore()) {
519 } else if (MCID.mayLoad()) {
StackSlotColoring.cpp 507 const MCInstrDesc &MCID = MII->getDesc();
524 const TargetRegisterClass *RC = TII->getRegClass(MCID, i, TRI);
569 const MCInstrDesc &MCID = MII->getDesc();
586 const TargetRegisterClass *RC = TII->getRegClass(MCID, i, TRI);
  /external/llvm/lib/Target/ARM/
ARMHazardRecognizer.cpp 22 const MCInstrDesc &MCID = MI->getDesc();
23 unsigned Domain = MCID.TSFlags & ARMII::DomainMask;
24 if (MCID.mayStore())
26 unsigned Opcode = MCID.getOpcode();
46 const MCInstrDesc &MCID = MI->getDesc();
47 if (LastMI && (MCID.TSFlags & ARMII::DomainMask) != ARMII::DomainGeneral) {
Thumb1RegisterInfo.cpp 240 const MCInstrDesc &MCID = TII.get(isSub ? ARM::tSUBi3 : ARM::tADDi3);
242 AddDefaultT1CC(BuildMI(MBB, MBBI, dl, MCID, DestReg)
290 const MCInstrDesc &MCID = TII.get(ExtraOpc);
291 AddDefaultPred(AddDefaultT1CC(BuildMI(MBB, MBBI, dl, MCID, DestReg))
359 const MCInstrDesc &MCID = TII.get(ARM::tRSB);
360 AddDefaultPred(AddDefaultT1CC(BuildMI(MBB, MBBI, dl, MCID, DestReg))
MLxExpansionPass.cpp 140 const MCInstrDesc &MCID = MI->getDesc();
141 unsigned Domain = MCID.TSFlags & ARMII::DomainMask;
142 if (MCID.mayStore())
144 unsigned Opcode = MCID.getOpcode();
276 const MCInstrDesc &MCID = MI->getDesc();
277 if (MCID.isBarrier()) {
284 unsigned Domain = MCID.TSFlags & ARMII::DomainMask;
294 if (!TII->isFpMLxInstruction(MCID.getOpcode(),
Thumb2ITBlockPass.cpp 143 const MCInstrDesc &MCID = MI->getDesc();
144 if (MCID.hasOptionalDef() &&
145 MI->getOperand(MCID.getNumOperands() - 1).getReg() == ARM::CPSR)
  /external/llvm/lib/Target/
TargetInstrInfo.cpp 31 TargetInstrInfo::getRegClass(const MCInstrDesc &MCID, unsigned OpNum,
33 if (OpNum >= MCID.getNumOperands())
36 short RegClass = MCID.OpInfo[OpNum].RegClass;
37 if (MCID.OpInfo[OpNum].isLookupPtrRegClass())
133 const MCInstrDesc &MCID = MI->getDesc();
134 if (!MCID.isTerminator()) return false;
137 if (MCID.isBranch() && !MCID.isBarrier())
139 if (!MCID.isPredicable())
  /external/llvm/lib/Target/MSP430/
MSP430InstrInfo.cpp 164 const MCInstrDesc &MCID = MI->getDesc();
165 if (!MCID.isTerminator()) return false;
168 if (MCID.isBranch() && !MCID.isBarrier())
170 if (!MCID.isPredicable())
  /external/llvm/lib/Target/Mips/
MipsDelaySlotFiller.cpp 177 MCInstrDesc MCID = candidate->getDesc();
180 if (MCID.mayLoad()) {
186 if (MCID.mayStore()) {
194 assert((!MCID.isCall() && !MCID.isReturn()) &&
223 MCInstrDesc MCID = MI->getDesc();
224 unsigned e = MCID.isCall() || MCID.isReturn() ? MCID.getNumOperands() :
228 if (MCID.isCall()
    [all...]
MipsInstrInfo.cpp 360 const MCInstrDesc &MCID = get(Opc);
361 MachineInstrBuilder MIB = BuildMI(&MBB, DL, MCID);
  /external/llvm/lib/Target/PowerPC/
PPCHazardRecognizers.cpp 27 const MCInstrDesc *MCID = DAG->getInstrDesc(SU);
28 if (!MCID) {
89 const MCInstrDesc &MCID = TII.get(Opcode);
91 isLoad = MCID.mayLoad();
92 isStore = MCID.mayStore();
94 uint64_t TSFlags = MCID.TSFlags;
PPCInstrInfo.cpp 330 const MCInstrDesc &MCID = get(Opc);
331 if (MCID.getNumOperands() == 3)
332 BuildMI(MBB, I, DL, MCID, DestReg)
335 BuildMI(MBB, I, DL, MCID, DestReg).addReg(SrcReg, getKillRegState(KillSrc));
  /external/llvm/lib/Target/SystemZ/
SystemZInstrBuilder.h 111 const MCInstrDesc &MCID = MI->getDesc();
113 if (MCID.mayLoad())
115 if (MCID.mayStore())
SystemZInstrInfo.cpp 206 const MCInstrDesc &MCID = MI->getDesc();
207 if (!MCID.isTerminator()) return false;
210 if (MCID.isBranch() && !MCID.isBarrier())
212 if (!MCID.isPredicable())
  /external/llvm/lib/Target/X86/
X86InstrBuilder.h 153 const MCInstrDesc &MCID = MI->getDesc();
155 if (MCID.mayLoad())
157 if (MCID.mayStore())
  /external/llvm/include/llvm/CodeGen/
MachineInstr.h 61 const MCInstrDesc *MCID; // Instruction descriptor.
93 /// MCID NULL and no operands.
103 explicit MachineInstr(const MCInstrDesc &MCID, bool NoImp = false);
108 MachineInstr(MachineBasicBlock *MBB, const MCInstrDesc &MCID);
113 explicit MachineInstr(const MCInstrDesc &MCID, const DebugLoc dl,
120 const MCInstrDesc &MCID);
191 const MCInstrDesc &getDesc() const { return *MCID; }
195 int getOpcode() const { return MCID->Opcode; }
532 void setDesc(const MCInstrDesc &tid) { MCID = &tid; }
  /external/llvm/lib/CodeGen/SelectionDAG/
InstrEmitter.cpp 285 const MCInstrDesc &MCID = MI->getDesc();
286 bool isOptDef = IIOpNum < MCID.getNumOperands() &&
287 MCID.OpInfo[IIOpNum].isOptionalDef();
297 assert((DstRC || (MCID.isVariadic() && IIOpNum >= MCID.getNumOperands())) &&
714 const MCInstrDesc &MCID = TII->get(F->getMachineOpcode());
715 UsedRegs.append(MCID.getImplicitUses(),
716 MCID.getImplicitUses() + MCID.getNumImplicitUses());
    [all...]
ScheduleDAGFast.cpp 252 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
253 for (unsigned i = 0; i != MCID.getNumOperands(); ++i) {
254 if (MCID.getOperandConstraint(i, MCOI::TIED_TO) != -1) {
259 if (MCID.isCommutable())
425 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
426 assert(MCID.ImplicitDefs && "Physical reg def must be in implicit def list!");
427 unsigned NumRes = MCID.getNumDefs();
428 for (const unsigned *ImpDef = MCID.getImplicitDefs(); *ImpDef; ++ImpDef) {
508 const MCInstrDesc &MCID = TII->get(Node->getMachineOpcode());
509 if (!MCID.ImplicitDefs
    [all...]
  /external/llvm/lib/Target/PTX/
PTXInstrInfo.cpp 58 const MCInstrDesc &MCID = get(map[i].opcode);
59 MachineInstr *MI = BuildMI(MBB, I, DL, MCID, DstReg).
80 const MCInstrDesc &MCID = get(map[i].opcode);
81 MachineInstr *MI = BuildMI(MBB, I, DL, MCID, DstReg).addReg(SrcReg);
  /external/llvm/include/llvm/MC/
MCInstrDesc.h 96 namespace MCID {
192 return Flags & (1 << MCID::Variadic);
198 return Flags & (1 << MCID::HasOptionalDef);
283 return Flags & (1 << MCID::Pseudo);
287 return Flags & (1 << MCID::Return);
291 return Flags & (1 << MCID::Call);
298 return Flags & (1 << MCID::Barrier);
320 return Flags & (1 << MCID::Terminator);
328 return Flags & (1 << MCID::Branch);
334 return Flags & (1 << MCID::IndirectBranch)
    [all...]

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