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      1 //===-- Thumb2ITBlockPass.cpp - Insert Thumb IT blocks ----------*- C++ -*-===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 
     10 #define DEBUG_TYPE "thumb2-it"
     11 #include "ARM.h"
     12 #include "ARMMachineFunctionInfo.h"
     13 #include "Thumb2InstrInfo.h"
     14 #include "llvm/CodeGen/MachineInstr.h"
     15 #include "llvm/CodeGen/MachineInstrBuilder.h"
     16 #include "llvm/CodeGen/MachineFunctionPass.h"
     17 #include "llvm/ADT/SmallSet.h"
     18 #include "llvm/ADT/Statistic.h"
     19 using namespace llvm;
     20 
     21 STATISTIC(NumITs,        "Number of IT blocks inserted");
     22 STATISTIC(NumMovedInsts, "Number of predicated instructions moved");
     23 
     24 namespace {
     25   class Thumb2ITBlockPass : public MachineFunctionPass {
     26     bool PreRegAlloc;
     27 
     28   public:
     29     static char ID;
     30     Thumb2ITBlockPass() : MachineFunctionPass(ID) {}
     31 
     32     const Thumb2InstrInfo *TII;
     33     const TargetRegisterInfo *TRI;
     34     ARMFunctionInfo *AFI;
     35 
     36     virtual bool runOnMachineFunction(MachineFunction &Fn);
     37 
     38     virtual const char *getPassName() const {
     39       return "Thumb IT blocks insertion pass";
     40     }
     41 
     42   private:
     43     bool MoveCopyOutOfITBlock(MachineInstr *MI,
     44                               ARMCC::CondCodes CC, ARMCC::CondCodes OCC,
     45                               SmallSet<unsigned, 4> &Defs,
     46                               SmallSet<unsigned, 4> &Uses);
     47     bool InsertITInstructions(MachineBasicBlock &MBB);
     48   };
     49   char Thumb2ITBlockPass::ID = 0;
     50 }
     51 
     52 /// TrackDefUses - Tracking what registers are being defined and used by
     53 /// instructions in the IT block. This also tracks "dependencies", i.e. uses
     54 /// in the IT block that are defined before the IT instruction.
     55 static void TrackDefUses(MachineInstr *MI,
     56                          SmallSet<unsigned, 4> &Defs,
     57                          SmallSet<unsigned, 4> &Uses,
     58                          const TargetRegisterInfo *TRI) {
     59   SmallVector<unsigned, 4> LocalDefs;
     60   SmallVector<unsigned, 4> LocalUses;
     61 
     62   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
     63     MachineOperand &MO = MI->getOperand(i);
     64     if (!MO.isReg())
     65       continue;
     66     unsigned Reg = MO.getReg();
     67     if (!Reg || Reg == ARM::ITSTATE || Reg == ARM::SP)
     68       continue;
     69     if (MO.isUse())
     70       LocalUses.push_back(Reg);
     71     else
     72       LocalDefs.push_back(Reg);
     73   }
     74 
     75   for (unsigned i = 0, e = LocalUses.size(); i != e; ++i) {
     76     unsigned Reg = LocalUses[i];
     77     Uses.insert(Reg);
     78     for (const unsigned *Subreg = TRI->getSubRegisters(Reg);
     79          *Subreg; ++Subreg)
     80       Uses.insert(*Subreg);
     81   }
     82 
     83   for (unsigned i = 0, e = LocalDefs.size(); i != e; ++i) {
     84     unsigned Reg = LocalDefs[i];
     85     Defs.insert(Reg);
     86     for (const unsigned *Subreg = TRI->getSubRegisters(Reg);
     87          *Subreg; ++Subreg)
     88       Defs.insert(*Subreg);
     89     if (Reg == ARM::CPSR)
     90       continue;
     91   }
     92 }
     93 
     94 static bool isCopy(MachineInstr *MI) {
     95   switch (MI->getOpcode()) {
     96   default:
     97     return false;
     98   case ARM::MOVr:
     99   case ARM::MOVr_TC:
    100   case ARM::tMOVr:
    101   case ARM::t2MOVr:
    102     return true;
    103   }
    104 }
    105 
    106 bool
    107 Thumb2ITBlockPass::MoveCopyOutOfITBlock(MachineInstr *MI,
    108                                       ARMCC::CondCodes CC, ARMCC::CondCodes OCC,
    109                                         SmallSet<unsigned, 4> &Defs,
    110                                         SmallSet<unsigned, 4> &Uses) {
    111   if (!isCopy(MI))
    112     return false;
    113   // llvm models select's as two-address instructions. That means a copy
    114   // is inserted before a t2MOVccr, etc. If the copy is scheduled in
    115   // between selects we would end up creating multiple IT blocks.
    116   assert(MI->getOperand(0).getSubReg() == 0 &&
    117          MI->getOperand(1).getSubReg() == 0 &&
    118          "Sub-register indices still around?");
    119 
    120   unsigned DstReg = MI->getOperand(0).getReg();
    121   unsigned SrcReg = MI->getOperand(1).getReg();
    122 
    123   // First check if it's safe to move it.
    124   if (Uses.count(DstReg) || Defs.count(SrcReg))
    125     return false;
    126 
    127   // If the CPSR is defined by this copy, then we don't want to move it. E.g.,
    128   // if we have:
    129   //
    130   //   movs  r1, r1
    131   //   rsb   r1, 0
    132   //   movs  r2, r2
    133   //   rsb   r2, 0
    134   //
    135   // we don't want this to be converted to:
    136   //
    137   //   movs  r1, r1
    138   //   movs  r2, r2
    139   //   itt   mi
    140   //   rsb   r1, 0
    141   //   rsb   r2, 0
    142   //
    143   const MCInstrDesc &MCID = MI->getDesc();
    144   if (MCID.hasOptionalDef() &&
    145       MI->getOperand(MCID.getNumOperands() - 1).getReg() == ARM::CPSR)
    146     return false;
    147 
    148   // Then peek at the next instruction to see if it's predicated on CC or OCC.
    149   // If not, then there is nothing to be gained by moving the copy.
    150   MachineBasicBlock::iterator I = MI; ++I;
    151   MachineBasicBlock::iterator E = MI->getParent()->end();
    152   while (I != E && I->isDebugValue())
    153     ++I;
    154   if (I != E) {
    155     unsigned NPredReg = 0;
    156     ARMCC::CondCodes NCC = llvm::getITInstrPredicate(I, NPredReg);
    157     if (NCC == CC || NCC == OCC)
    158       return true;
    159   }
    160   return false;
    161 }
    162 
    163 bool Thumb2ITBlockPass::InsertITInstructions(MachineBasicBlock &MBB) {
    164   bool Modified = false;
    165 
    166   SmallSet<unsigned, 4> Defs;
    167   SmallSet<unsigned, 4> Uses;
    168   MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
    169   while (MBBI != E) {
    170     MachineInstr *MI = &*MBBI;
    171     DebugLoc dl = MI->getDebugLoc();
    172     unsigned PredReg = 0;
    173     ARMCC::CondCodes CC = llvm::getITInstrPredicate(MI, PredReg);
    174     if (CC == ARMCC::AL) {
    175       ++MBBI;
    176       continue;
    177     }
    178 
    179     Defs.clear();
    180     Uses.clear();
    181     TrackDefUses(MI, Defs, Uses, TRI);
    182 
    183     // Insert an IT instruction.
    184     MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII->get(ARM::t2IT))
    185       .addImm(CC);
    186 
    187     // Add implicit use of ITSTATE to IT block instructions.
    188     MI->addOperand(MachineOperand::CreateReg(ARM::ITSTATE, false/*ifDef*/,
    189                                              true/*isImp*/, false/*isKill*/));
    190 
    191     MachineInstr *LastITMI = MI;
    192     MachineBasicBlock::iterator InsertPos = MIB;
    193     ++MBBI;
    194 
    195     // Form IT block.
    196     ARMCC::CondCodes OCC = ARMCC::getOppositeCondition(CC);
    197     unsigned Mask = 0, Pos = 3;
    198     // Branches, including tricky ones like LDM_RET, need to end an IT
    199     // block so check the instruction we just put in the block.
    200     for (; MBBI != E && Pos &&
    201            (!MI->getDesc().isBranch() && !MI->getDesc().isReturn()) ; ++MBBI) {
    202       if (MBBI->isDebugValue())
    203         continue;
    204 
    205       MachineInstr *NMI = &*MBBI;
    206       MI = NMI;
    207 
    208       unsigned NPredReg = 0;
    209       ARMCC::CondCodes NCC = llvm::getITInstrPredicate(NMI, NPredReg);
    210       if (NCC == CC || NCC == OCC) {
    211         Mask |= (NCC & 1) << Pos;
    212         // Add implicit use of ITSTATE.
    213         NMI->addOperand(MachineOperand::CreateReg(ARM::ITSTATE, false/*ifDef*/,
    214                                                true/*isImp*/, false/*isKill*/));
    215         LastITMI = NMI;
    216       } else {
    217         if (NCC == ARMCC::AL &&
    218             MoveCopyOutOfITBlock(NMI, CC, OCC, Defs, Uses)) {
    219           --MBBI;
    220           MBB.remove(NMI);
    221           MBB.insert(InsertPos, NMI);
    222           ++NumMovedInsts;
    223           continue;
    224         }
    225         break;
    226       }
    227       TrackDefUses(NMI, Defs, Uses, TRI);
    228       --Pos;
    229     }
    230 
    231     // Finalize IT mask.
    232     Mask |= (1 << Pos);
    233     // Tag along (firstcond[0] << 4) with the mask.
    234     Mask |= (CC & 1) << 4;
    235     MIB.addImm(Mask);
    236 
    237     // Last instruction in IT block kills ITSTATE.
    238     LastITMI->findRegisterUseOperand(ARM::ITSTATE)->setIsKill();
    239 
    240     Modified = true;
    241     ++NumITs;
    242   }
    243 
    244   return Modified;
    245 }
    246 
    247 bool Thumb2ITBlockPass::runOnMachineFunction(MachineFunction &Fn) {
    248   const TargetMachine &TM = Fn.getTarget();
    249   AFI = Fn.getInfo<ARMFunctionInfo>();
    250   TII = static_cast<const Thumb2InstrInfo*>(TM.getInstrInfo());
    251   TRI = TM.getRegisterInfo();
    252 
    253   if (!AFI->isThumbFunction())
    254     return false;
    255 
    256   bool Modified = false;
    257   for (MachineFunction::iterator MFI = Fn.begin(), E = Fn.end(); MFI != E; ) {
    258     MachineBasicBlock &MBB = *MFI;
    259     ++MFI;
    260     Modified |= InsertITInstructions(MBB);
    261   }
    262 
    263   if (Modified)
    264     AFI->setHasITBlocks(true);
    265 
    266   return Modified;
    267 }
    268 
    269 /// createThumb2ITBlockPass - Returns an instance of the Thumb2 IT blocks
    270 /// insertion pass.
    271 FunctionPass *llvm::createThumb2ITBlockPass() {
    272   return new Thumb2ITBlockPass();
    273 }
    274