| /external/llvm/lib/CodeGen/ |
| RegisterCoalescer.h | 32 /// DstReg - The register that will be left after coalescing. It can be a
34 unsigned DstReg;
36 /// SrcReg - the virtual register that will be coalesced into dstReg.
39 /// subReg_ - The subregister index of srcReg in DstReg. It is possible the
40 /// coalesce SrcReg into a subreg of the larger DstReg when DstReg is a
50 /// Flipped - True when DstReg and SrcReg are reversed from the oriignal
54 /// NewRC - The register class of the coalesced register, or NULL if DstReg
60 : TII(tii), TRI(tri), DstReg(0), SrcReg(0), SubIdx(0),
67 /// flip - Swap SrcReg and DstReg. Return false if swapping is impossibl
[all...] |
| OptimizePHIs.cpp | 88 unsigned DstReg = MI->getOperand(0).getReg();
101 if (SrcReg == DstReg)
131 unsigned DstReg = MI->getOperand(0).getReg();
132 assert(TargetRegisterInfo::isVirtualRegister(DstReg) &&
143 for (MachineRegisterInfo::use_iterator I = MRI->use_begin(DstReg),
|
| TwoAddressInstructionPass.cpp | 130 void ScanUses(unsigned DstReg, MachineBasicBlock *MBB,
136 void CoalesceExtSubRegs(SmallVector<unsigned,4> &Srcs, unsigned DstReg);
393 unsigned &SrcReg, unsigned &DstReg,
396 DstReg = 0;
398 DstReg = MI.getOperand(0).getReg();
401 DstReg = MI.getOperand(0).getReg();
407 IsDstPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
442 unsigned SrcReg, DstReg;
445 if (!isCopyToReg(*DefMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys))
453 static bool isTwoAddrUse(MachineInstr &MI, unsigned Reg, unsigned &DstReg) {
[all...] |
| ExpandPostRAPseudos.cpp | 57 void TransferDeadFlag(MachineInstr *MI, unsigned DstReg,
69 /// TransferDeadFlag - MI is a pseudo-instruction with DstReg dead,
73 ExpandPostRA::TransferDeadFlag(MachineInstr *MI, unsigned DstReg,
77 if (MII->addRegisterDead(DstReg, TRI))
107 unsigned DstReg = MI->getOperand(0).getReg();
113 unsigned DstSubReg = TRI->getSubReg(DstReg, SubIdx);
115 assert(TargetRegisterInfo::isPhysicalRegister(DstReg) &&
127 if (DstReg != InsReg) {
|
| RegisterCoalescer.cpp | 113 /// JoinCopy - Attempt to join intervals corresponding to SrcReg/DstReg,
147 unsigned DstReg, MachineInstr *CopyMI);
155 unsigned DstReg,
160 /// UpdateRegDefsUses - Replace all defs and uses of SrcReg to DstReg and
161 /// update the subregister number if it is not zero. If DstReg is a
172 /// RemoveCopyFlag - If DstReg is no longer defined by CopyMI, clear the
173 /// VNInfo copy flag for DstReg and all aliases.
174 void RemoveCopyFlag(unsigned DstReg, const MachineInstr *CopyMI);
243 SrcReg = DstReg = SubIdx = 0;
321 DstReg = Dst
[all...] |
| PeepholeOptimizer.cpp | 134 unsigned SrcReg, DstReg, SubIdx;
135 if (!TII->isCoalescableExtInstr(*MI, SrcReg, DstReg, SubIdx))
138 if (TargetRegisterInfo::isPhysicalRegister(DstReg) ||
150 UI = MRI->use_nodbg_begin(DstReg);
229 UI = MRI->use_nodbg_begin(DstReg);
246 .addReg(DstReg, 0, SubIdx);
|
| MachineSink.cpp | 115 unsigned DstReg = MI->getOperand(0).getReg();
117 !TargetRegisterInfo::isVirtualRegister(DstReg) ||
122 const TargetRegisterClass *DRC = MRI->getRegClass(DstReg);
131 MRI->replaceRegWith(DstReg, SrcReg);
|
| LiveDebugVariables.cpp | 566 unsigned DstReg = MI->getOperand(0).getReg();
572 if (!TargetRegisterInfo::isVirtualRegister(DstReg))
582 if (!LIS.hasInterval(DstReg))
584 LiveInterval *DstLI = &LIS.getInterval(DstReg);
[all...] |
| StackSlotColoring.cpp | 616 if (unsigned DstReg = TII->isLoadFromStackSlot(MI, OldFI)) {
617 if (PropagateForward(MI, MBB, DstReg, Reg)) {
623 DstReg).addReg(Reg);
|
| InlineSpiller.cpp | 770 if (unsigned DstReg = isFullCopyOf(MI, Reg)) {
771 if (isSibling(DstReg)) {
772 LiveInterval &DstLI = LIS.getInterval(DstReg);
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsExpandPseudo.cpp | 88 unsigned DstReg = I->getOperand(0).getReg();
93 TM.getRegisterInfo()->getSubRegisters(DstReg);
103 unsigned DstReg = I->getOperand(0).getReg();
110 BuildMI(MBB, I, dl, Mfc1Tdd, DstReg).addReg(*(SubReg + N));
|
| /external/llvm/lib/Target/XCore/ |
| XCoreRegisterInfo.h | 32 unsigned DstReg, int64_t Value, DebugLoc dl) const;
40 unsigned DstReg, int Offset, DebugLoc dl) const;
|
| XCoreRegisterInfo.cpp | 313 unsigned DstReg, int64_t Value, DebugLoc dl) const {
320 BuildMI(MBB, I, dl, TII.get(Opcode), DstReg).addImm(Value);
|
| XCoreFrameLowering.cpp | 47 unsigned DstReg, int Offset, DebugLoc dl,
55 BuildMI(MBB, I, dl, TII.get(Opcode), DstReg)
|
| /external/llvm/lib/Target/PTX/ |
| PTXInstrInfo.h | 42 unsigned DstReg, unsigned SrcReg,
47 unsigned DstReg, unsigned SrcReg,
53 unsigned &SrcReg, unsigned &DstReg,
|
| PTXInstrInfo.cpp | 49 unsigned DstReg, unsigned SrcReg,
53 //assert(MRI.getRegClass(SrcReg) == MRI.getRegClass(DstReg) &&
57 if (map[i].cls == MRI.getRegClass(DstReg)) {
59 MachineInstr *MI = BuildMI(MBB, I, DL, MCID, DstReg).
71 unsigned DstReg, unsigned SrcReg,
81 MachineInstr *MI = BuildMI(MBB, I, DL, MCID, DstReg).addReg(SrcReg);
90 unsigned &SrcReg, unsigned &DstReg,
105 DstReg = MI.getOperand(0).getReg();
|
| /external/llvm/lib/Target/MSP430/ |
| MSP430RegisterInfo.cpp | 207 unsigned DstReg = MI.getOperand(0).getReg();
209 BuildMI(MBB, llvm::next(II), dl, TII.get(MSP430::SUB16ri), DstReg)
210 .addReg(DstReg).addImm(-Offset);
212 BuildMI(MBB, llvm::next(II), dl, TII.get(MSP430::ADD16ri), DstReg)
213 .addReg(DstReg).addImm(Offset);
|
| /external/llvm/lib/Target/ARM/ |
| ARMExpandPseudoInsts.cpp | 422 unsigned DstReg = MI.getOperand(OpIdx++).getReg();
424 GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3);
461 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
546 unsigned DstReg = 0;
550 DstReg = MI.getOperand(OpIdx++).getReg();
551 GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3);
600 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
649 unsigned DstReg = MI.getOperand(0).getReg();
658 LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVi), DstReg);
660 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)
[all...] |
| Thumb2ITBlockPass.cpp | 120 unsigned DstReg = MI->getOperand(0).getReg();
124 if (Uses.count(DstReg) || Defs.count(SrcReg))
|
| MLxExpansionPass.cpp | 209 unsigned DstReg = MI->getOperand(0).getReg();
233 .addReg(DstReg, getDefRegState(true) | getDeadRegState(DstDead));
|
| ARMAsmPrinter.cpp | [all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCFrameLowering.cpp | 132 unsigned DstReg = MI->getOperand(0).getReg();
135 if (DstReg != SrcReg)
136 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
140 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
144 if (DstReg != SrcReg)
145 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
149 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
153 if (DstReg != SrcReg)
154 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
158 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86InstrInfo.h | 167 unsigned &SrcReg, unsigned &DstReg,
|
| /external/llvm/include/llvm/CodeGen/ |
| MachineInstr.h | 477 unsigned DstReg) const;
|
| /external/llvm/include/llvm/Target/ |
| TargetInstrInfo.h | 110 unsigned &SrcReg, unsigned &DstReg,
[all...] |
