| /external/llvm/lib/Target/CellSPU/ |
| SPUInstrBuilder.h | 33 addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset = 0,
36 return MIB.addImm(Offset).addFrameIndex(FI);
38 return MIB.addFrameIndex(FI).addImm(Offset);
|
| SPUInstrInfo.cpp | 360 MachineInstrBuilder MIB;
368 MIB = BuildMI(&MBB, DL, get(SPU::HBR_LABEL)).addSym(branchLabel);
374 MIB = BuildMI(&MBB, DL, get(SPU::BR));
375 MIB.addMBB(TBB);
378 DEBUG((*MIB).dump());
382 MIB = BuildMI( MBB, findHBRPosition(MBB), DL, get(SPU::HBRA));
383 MIB.addSym(branchLabel);
384 MIB.addMBB(TBB);
388 MIB = BuildMI(&MBB, DL, get(Cond[0].getImm()));
389 MIB.addReg(Cond[1].getReg()).addMBB(TBB)
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCInstrBuilder.h | 33 addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset = 0,
36 return MIB.addImm(Offset).addFrameIndex(FI);
38 return MIB.addFrameIndex(FI).addImm(Offset);
|
| /external/llvm/lib/Target/SystemZ/ |
| SystemZInstrBuilder.h | 59 addDirectMem(const MachineInstrBuilder &MIB, unsigned Reg) {
62 return MIB.addReg(Reg).addImm(0).addReg(0);
66 addOffset(const MachineInstrBuilder &MIB, int Offset) {
67 return MIB.addImm(Offset).addReg(0);
75 addRegOffset(const MachineInstrBuilder &MIB,
77 return addOffset(MIB.addReg(Reg, getKillRegState(isKill)), Offset);
83 addRegReg(const MachineInstrBuilder &MIB,
85 return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(0)
90 addFullAddress(const MachineInstrBuilder &MIB, const SystemZAddressMode &AM) {
92 MIB.addReg(AM.Base.Reg)
[all...] |
| SystemZFrameLowering.cpp | 264 MachineInstrBuilder MIB =
269 MIB.addReg(SystemZ::R15D).addImm(StartOffset);
271 MIB.addReg(0);
272 MIB.addReg(LowReg, RegState::Kill);
274 MIB.addReg(HighReg, RegState::Kill);
282 MIB.addReg(Reg, RegState::ImplicitKill);
329 MachineInstrBuilder MIB =
333 MIB.addReg(LowReg, RegState::Define);
335 MIB.addReg(HighReg, RegState::Define);
337 MIB.addReg(hasFP(MF) ? SystemZ::R11D : SystemZ::R15D)
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86InstrBuilder.h | 91 addDirectMem(const MachineInstrBuilder &MIB, unsigned Reg) {
94 return MIB.addReg(Reg).addImm(1).addReg(0).addImm(0).addReg(0);
99 addOffset(const MachineInstrBuilder &MIB, int Offset) {
100 return MIB.addImm(1).addReg(0).addImm(Offset).addReg(0);
108 addRegOffset(const MachineInstrBuilder &MIB,
110 return addOffset(MIB.addReg(Reg, getKillRegState(isKill)), Offset);
115 static inline const MachineInstrBuilder &addRegReg(const MachineInstrBuilder &MIB,
118 return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(1)
123 addFullAddress(const MachineInstrBuilder &MIB,
128 MIB.addReg(AM.Base.Reg)
[all...] |
| X86InstrInfo.cpp | [all...] |
| X86FastISel.cpp | [all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMExpandPseudoInsts.cpp | 417 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
425 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead))
428 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead));
430 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead));
433 MIB.addOperand(MI.getOperand(OpIdx++));
436 MIB.addOperand(MI.getOperand(OpIdx++));
437 MIB.addOperand(MI.getOperand(OpIdx++));
440 MIB.addOperand(MI.getOperand(OpIdx++));
450 MIB.addOperand(MI.getOperand(OpIdx++));
451 MIB.addOperand(MI.getOperand(OpIdx++))
[all...] |
| Thumb1RegisterInfo.cpp | 129 MachineInstrBuilder MIB =
132 MIB = AddDefaultT1CC(MIB);
134 MIB.addReg(BaseReg).addReg(LdReg, RegState::Kill);
136 MIB.addReg(LdReg).addReg(BaseReg, RegState::Kill);
137 AddDefaultPred(MIB);
241 const MachineInstrBuilder MIB =
244 AddDefaultPred(MIB.addReg(BaseReg, RegState::Kill).addImm(ThisVal));
260 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);
262 MIB = AddDefaultT1CC(MIB)
[all...] |
| Thumb2SizeReduction.cpp | 445 MachineInstrBuilder MIB = BuildMI(MBB, *MI, dl, TII->get(Opc));
447 MIB.addOperand(MI->getOperand(0));
448 MIB.addOperand(MI->getOperand(1));
451 MIB.addImm(OffsetImm / Scale);
456 MIB.addReg(OffsetReg, getKillRegState(OffsetKill));
461 MIB.addOperand(MI->getOperand(OpNum));
464 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
467 MIB.setMIFlags(MI->getFlags());
469 DEBUG(errs() << "Converted 32-bit: " << *MI << " to 16-bit: " << *MIB);
505 MachineInstrBuilder MIB = BuildMI(MBB, *MI, MI->getDebugLoc()
[all...] |
| ARMBaseInstrInfo.h | 294 const MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) {
295 return MIB.addImm((int64_t)ARMCC::AL).addReg(0);
299 const MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) {
300 return MIB.addReg(0);
304 const MachineInstrBuilder &AddDefaultT1CC(const MachineInstrBuilder &MIB,
306 return MIB.addReg(ARM::CPSR, getDefRegState(true) | getDeadRegState(isDead));
310 const MachineInstrBuilder &AddNoT1CC(const MachineInstrBuilder &MIB) {
311 return MIB.addReg(0);
|
| Thumb1FrameLowering.cpp | 324 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(ARM::tPUSH));
325 AddDefaultPred(MIB);
343 MIB.addReg(Reg, getKillRegState(isKill));
345 MIB.setMIFlags(MachineInstr::FrameSetup);
363 MachineInstrBuilder MIB = BuildMI(MF, DL, TII.get(ARM::tPOP));
364 AddDefaultPred(MIB);
374 (*MIB).setDesc(TII.get(ARM::tPOP_RET));
377 MIB.addReg(Reg, getDefRegState(true));
383 MBB.insert(MI, &*MIB);
385 MF.DeleteMachineInstr(MIB);
[all...] |
| MLxExpansionPass.cpp | 225 MachineInstrBuilder MIB = BuildMI(MBB, *MI, MI->getDebugLoc(), MCID1, TmpReg)
229 MIB.addImm(LaneImm);
230 MIB.addImm(Pred).addReg(PredReg);
232 MIB = BuildMI(MBB, *MI, MI->getDebugLoc(), MCID2)
237 MIB.addReg(TmpReg, getKillRegState(true))
240 MIB.addReg(AccReg).addReg(TmpReg, getKillRegState(true));
242 MIB.addImm(Pred).addReg(PredReg);
|
| ARMFastISel.cpp | 208 const MachineInstrBuilder &AddOptionalDefs(const MachineInstrBuilder &MIB);
210 const MachineInstrBuilder &MIB,
257 ARMFastISel::AddOptionalDefs(const MachineInstrBuilder &MIB) {
258 MachineInstr *MI = &*MIB;
264 AddDefaultPred(MIB);
271 AddDefaultT1CC(MIB);
273 AddDefaultCC(MIB);
275 return MIB;
607 MachineInstrBuilder MIB;
611 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), DestReg
[all...] |
| ARMBaseInstrInfo.cpp | 655 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg);
656 MIB.addReg(SrcReg, getKillRegState(KillSrc));
658 MIB.addReg(SrcReg, getKillRegState(KillSrc));
659 AddDefaultPred(MIB);
690 MachineInstrBuilder &AddDReg(MachineInstrBuilder &MIB,
694 return MIB.addReg(Reg, State);
697 return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State);
698 return MIB.addReg(Reg, State, SubIdx);
766 MachineInstrBuilder MIB =
770 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI)
[all...] |
| ARMFrameLowering.cpp | 199 MachineInstrBuilder MIB =
203 AddDefaultCC(AddDefaultPred(MIB));
408 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(TCOpcode));
410 MIB.addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
414 MIB.addExternalSymbol(JumpTarget.getSymbolName(),
419 if (STI.isThumb()) MIB.addImm(ARMCC::AL).addReg(0);
585 MachineInstrBuilder MIB =
589 MIB.addReg(Regs[i].first, getKillRegState(Regs[i].second));
591 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(StrOpc),
596 AddDefaultPred(MIB);
[all...] |
| Thumb2ITBlockPass.cpp | 184 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII->get(ARM::t2IT))
192 MachineBasicBlock::iterator InsertPos = MIB;
235 MIB.addImm(Mask);
|
| ARMLoadStoreOptimizer.cpp | 355 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII->get(Opcode))
359 MIB = MIB.addReg(Regs[i].first, getDefRegState(isDef)
747 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII->get(NewOpc))
754 MIB.addOperand(MI->getOperand(OpNum));
757 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
[all...] |
| Thumb2InstrInfo.cpp | 276 MachineInstrBuilder MIB =
281 AddDefaultCC(MIB);
408 MachineInstrBuilder MIB(&MI);
409 AddDefaultPred(MIB);
|
| /external/llvm/lib/Target/Mips/ |
| MipsInstrInfo.cpp | 153 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc));
156 MIB.addReg(DestReg, RegState::Define);
159 MIB.addReg(ZeroReg);
162 MIB.addReg(SrcReg, getKillRegState(KillSrc));
219 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Mips::DBG_VALUE))
221 return &*MIB;
361 MachineInstrBuilder MIB = BuildMI(&MBB, DL, MCID);
364 MIB.addReg(Cond[i].getReg());
366 MIB.addMBB(TBB);
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| InstrEmitter.cpp | 615 MachineInstrBuilder MIB = BuildMI(*MF, DL, II);
626 MIB.addReg(0U); // undef
628 AddOperand(&*MIB, Op, (*MIB).getNumOperands(), &II, VRBaseMap,
634 MIB.addCImm(CI);
636 MIB.addImm(CI->getSExtValue());
638 MIB.addFPImm(CF);
642 MIB.addReg(0U);
646 MIB.addReg(0U);
649 MIB.addImm(Offset).addMetadata(MDPtr)
[all...] |
| /external/llvm/lib/Target/MBlaze/ |
| MBlazeFrameLowering.cpp | 61 MachineInstr::mop_iterator MIB = MBB->operands_begin();
64 for (MachineInstr::mop_iterator MII = MIB; MII != MIE; ++MII) {
101 MachineBasicBlock::iterator MIB = MBB->begin();
123 for (MachineBasicBlock::iterator I=MIB; I != MIE; ++I) {
173 for (MachineBasicBlock::iterator I=MIB; I != MIE; ++I) {
|
| /external/llvm/lib/CodeGen/ |
| MachineSSAUpdater.cpp | 190 MachineInstrBuilder MIB(InsertedPHI);
192 MIB.addReg(PredValues[i].second).addMBB(PredValues[i].first);
|
| /external/llvm/lib/Target/XCore/ |
| XCoreInstrInfo.cpp | 393 MachineInstrBuilder MIB = BuildMI(MF, DL, get(XCore::DBG_VALUE))
395 return &*MIB;
|
