Home | History | Annotate | Download | only in CellSPU
      1 //===- SPUInstrInfo.cpp - Cell SPU Instruction Information ----------------===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // This file contains the Cell SPU implementation of the TargetInstrInfo class.
     11 //
     12 //===----------------------------------------------------------------------===//
     13 
     14 #include "SPUInstrInfo.h"
     15 #include "SPUInstrBuilder.h"
     16 #include "SPUTargetMachine.h"
     17 #include "SPUHazardRecognizers.h"
     18 #include "llvm/CodeGen/MachineInstrBuilder.h"
     19 #include "llvm/MC/MCContext.h"
     20 #include "llvm/Support/Debug.h"
     21 #include "llvm/Support/ErrorHandling.h"
     22 #include "llvm/Support/TargetRegistry.h"
     23 #include "llvm/Support/raw_ostream.h"
     24 
     25 #define GET_INSTRINFO_CTOR
     26 #include "SPUGenInstrInfo.inc"
     27 
     28 using namespace llvm;
     29 
     30 namespace {
     31   //! Predicate for an unconditional branch instruction
     32   inline bool isUncondBranch(const MachineInstr *I) {
     33     unsigned opc = I->getOpcode();
     34 
     35     return (opc == SPU::BR
     36             || opc == SPU::BRA
     37             || opc == SPU::BI);
     38   }
     39 
     40   //! Predicate for a conditional branch instruction
     41   inline bool isCondBranch(const MachineInstr *I) {
     42     unsigned opc = I->getOpcode();
     43 
     44     return (opc == SPU::BRNZr32
     45             || opc == SPU::BRNZv4i32
     46             || opc == SPU::BRZr32
     47             || opc == SPU::BRZv4i32
     48             || opc == SPU::BRHNZr16
     49             || opc == SPU::BRHNZv8i16
     50             || opc == SPU::BRHZr16
     51             || opc == SPU::BRHZv8i16);
     52   }
     53 }
     54 
     55 SPUInstrInfo::SPUInstrInfo(SPUTargetMachine &tm)
     56   : SPUGenInstrInfo(SPU::ADJCALLSTACKDOWN, SPU::ADJCALLSTACKUP),
     57     TM(tm),
     58     RI(*TM.getSubtargetImpl(), *this)
     59 { /* NOP */ }
     60 
     61 /// CreateTargetHazardRecognizer - Return the hazard recognizer to use for
     62 /// this target when scheduling the DAG.
     63 ScheduleHazardRecognizer *SPUInstrInfo::CreateTargetHazardRecognizer(
     64   const TargetMachine *TM,
     65   const ScheduleDAG *DAG) const {
     66   const TargetInstrInfo *TII = TM->getInstrInfo();
     67   assert(TII && "No InstrInfo?");
     68   return new SPUHazardRecognizer(*TII);
     69 }
     70 
     71 unsigned
     72 SPUInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
     73                                   int &FrameIndex) const {
     74   switch (MI->getOpcode()) {
     75   default: break;
     76   case SPU::LQDv16i8:
     77   case SPU::LQDv8i16:
     78   case SPU::LQDv4i32:
     79   case SPU::LQDv4f32:
     80   case SPU::LQDv2f64:
     81   case SPU::LQDr128:
     82   case SPU::LQDr64:
     83   case SPU::LQDr32:
     84   case SPU::LQDr16: {
     85     const MachineOperand MOp1 = MI->getOperand(1);
     86     const MachineOperand MOp2 = MI->getOperand(2);
     87     if (MOp1.isImm() && MOp2.isFI()) {
     88       FrameIndex = MOp2.getIndex();
     89       return MI->getOperand(0).getReg();
     90     }
     91     break;
     92   }
     93   }
     94   return 0;
     95 }
     96 
     97 unsigned
     98 SPUInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
     99                                  int &FrameIndex) const {
    100   switch (MI->getOpcode()) {
    101   default: break;
    102   case SPU::STQDv16i8:
    103   case SPU::STQDv8i16:
    104   case SPU::STQDv4i32:
    105   case SPU::STQDv4f32:
    106   case SPU::STQDv2f64:
    107   case SPU::STQDr128:
    108   case SPU::STQDr64:
    109   case SPU::STQDr32:
    110   case SPU::STQDr16:
    111   case SPU::STQDr8: {
    112     const MachineOperand MOp1 = MI->getOperand(1);
    113     const MachineOperand MOp2 = MI->getOperand(2);
    114     if (MOp1.isImm() && MOp2.isFI()) {
    115       FrameIndex = MOp2.getIndex();
    116       return MI->getOperand(0).getReg();
    117     }
    118     break;
    119   }
    120   }
    121   return 0;
    122 }
    123 
    124 void SPUInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
    125                                MachineBasicBlock::iterator I, DebugLoc DL,
    126                                unsigned DestReg, unsigned SrcReg,
    127                                bool KillSrc) const
    128 {
    129   // We support cross register class moves for our aliases, such as R3 in any
    130   // reg class to any other reg class containing R3.  This is required because
    131   // we instruction select bitconvert i64 -> f64 as a noop for example, so our
    132   // types have no specific meaning.
    133 
    134   BuildMI(MBB, I, DL, get(SPU::LRr128), DestReg)
    135     .addReg(SrcReg, getKillRegState(KillSrc));
    136 }
    137 
    138 void
    139 SPUInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
    140                                   MachineBasicBlock::iterator MI,
    141                                   unsigned SrcReg, bool isKill, int FrameIdx,
    142                                   const TargetRegisterClass *RC,
    143                                   const TargetRegisterInfo *TRI) const
    144 {
    145   unsigned opc;
    146   bool isValidFrameIdx = (FrameIdx < SPUFrameLowering::maxFrameOffset());
    147   if (RC == SPU::GPRCRegisterClass) {
    148     opc = (isValidFrameIdx ? SPU::STQDr128 : SPU::STQXr128);
    149   } else if (RC == SPU::R64CRegisterClass) {
    150     opc = (isValidFrameIdx ? SPU::STQDr64 : SPU::STQXr64);
    151   } else if (RC == SPU::R64FPRegisterClass) {
    152     opc = (isValidFrameIdx ? SPU::STQDr64 : SPU::STQXr64);
    153   } else if (RC == SPU::R32CRegisterClass) {
    154     opc = (isValidFrameIdx ? SPU::STQDr32 : SPU::STQXr32);
    155   } else if (RC == SPU::R32FPRegisterClass) {
    156     opc = (isValidFrameIdx ? SPU::STQDr32 : SPU::STQXr32);
    157   } else if (RC == SPU::R16CRegisterClass) {
    158     opc = (isValidFrameIdx ? SPU::STQDr16 : SPU::STQXr16);
    159   } else if (RC == SPU::R8CRegisterClass) {
    160     opc = (isValidFrameIdx ? SPU::STQDr8 : SPU::STQXr8);
    161   } else if (RC == SPU::VECREGRegisterClass) {
    162     opc = (isValidFrameIdx) ? SPU::STQDv16i8 : SPU::STQXv16i8;
    163   } else {
    164     llvm_unreachable("Unknown regclass!");
    165   }
    166 
    167   DebugLoc DL;
    168   if (MI != MBB.end()) DL = MI->getDebugLoc();
    169   addFrameReference(BuildMI(MBB, MI, DL, get(opc))
    170                     .addReg(SrcReg, getKillRegState(isKill)), FrameIdx);
    171 }
    172 
    173 void
    174 SPUInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
    175                                    MachineBasicBlock::iterator MI,
    176                                    unsigned DestReg, int FrameIdx,
    177                                    const TargetRegisterClass *RC,
    178                                    const TargetRegisterInfo *TRI) const
    179 {
    180   unsigned opc;
    181   bool isValidFrameIdx = (FrameIdx < SPUFrameLowering::maxFrameOffset());
    182   if (RC == SPU::GPRCRegisterClass) {
    183     opc = (isValidFrameIdx ? SPU::LQDr128 : SPU::LQXr128);
    184   } else if (RC == SPU::R64CRegisterClass) {
    185     opc = (isValidFrameIdx ? SPU::LQDr64 : SPU::LQXr64);
    186   } else if (RC == SPU::R64FPRegisterClass) {
    187     opc = (isValidFrameIdx ? SPU::LQDr64 : SPU::LQXr64);
    188   } else if (RC == SPU::R32CRegisterClass) {
    189     opc = (isValidFrameIdx ? SPU::LQDr32 : SPU::LQXr32);
    190   } else if (RC == SPU::R32FPRegisterClass) {
    191     opc = (isValidFrameIdx ? SPU::LQDr32 : SPU::LQXr32);
    192   } else if (RC == SPU::R16CRegisterClass) {
    193     opc = (isValidFrameIdx ? SPU::LQDr16 : SPU::LQXr16);
    194   } else if (RC == SPU::R8CRegisterClass) {
    195     opc = (isValidFrameIdx ? SPU::LQDr8 : SPU::LQXr8);
    196   } else if (RC == SPU::VECREGRegisterClass) {
    197     opc = (isValidFrameIdx) ? SPU::LQDv16i8 : SPU::LQXv16i8;
    198   } else {
    199     llvm_unreachable("Unknown regclass in loadRegFromStackSlot!");
    200   }
    201 
    202   DebugLoc DL;
    203   if (MI != MBB.end()) DL = MI->getDebugLoc();
    204   addFrameReference(BuildMI(MBB, MI, DL, get(opc), DestReg), FrameIdx);
    205 }
    206 
    207 //! Branch analysis
    208 /*!
    209   \note This code was kiped from PPC. There may be more branch analysis for
    210   CellSPU than what's currently done here.
    211  */
    212 bool
    213 SPUInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
    214                             MachineBasicBlock *&FBB,
    215                             SmallVectorImpl<MachineOperand> &Cond,
    216                             bool AllowModify) const {
    217   // If the block has no terminators, it just falls into the block after it.
    218   MachineBasicBlock::iterator I = MBB.end();
    219   if (I == MBB.begin())
    220     return false;
    221   --I;
    222   while (I->isDebugValue()) {
    223     if (I == MBB.begin())
    224       return false;
    225     --I;
    226   }
    227   if (!isUnpredicatedTerminator(I))
    228     return false;
    229 
    230   // Get the last instruction in the block.
    231   MachineInstr *LastInst = I;
    232 
    233   // If there is only one terminator instruction, process it.
    234   if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
    235     if (isUncondBranch(LastInst)) {
    236       // Check for jump tables
    237       if (!LastInst->getOperand(0).isMBB())
    238         return true;
    239       TBB = LastInst->getOperand(0).getMBB();
    240       return false;
    241     } else if (isCondBranch(LastInst)) {
    242       // Block ends with fall-through condbranch.
    243       TBB = LastInst->getOperand(1).getMBB();
    244       DEBUG(errs() << "Pushing LastInst:               ");
    245       DEBUG(LastInst->dump());
    246       Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
    247       Cond.push_back(LastInst->getOperand(0));
    248       return false;
    249     }
    250     // Otherwise, don't know what this is.
    251     return true;
    252   }
    253 
    254   // Get the instruction before it if it's a terminator.
    255   MachineInstr *SecondLastInst = I;
    256 
    257   // If there are three terminators, we don't know what sort of block this is.
    258   if (SecondLastInst && I != MBB.begin() &&
    259       isUnpredicatedTerminator(--I))
    260     return true;
    261 
    262   // If the block ends with a conditional and unconditional branch, handle it.
    263   if (isCondBranch(SecondLastInst) && isUncondBranch(LastInst)) {
    264     TBB =  SecondLastInst->getOperand(1).getMBB();
    265     DEBUG(errs() << "Pushing SecondLastInst:         ");
    266     DEBUG(SecondLastInst->dump());
    267     Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
    268     Cond.push_back(SecondLastInst->getOperand(0));
    269     FBB = LastInst->getOperand(0).getMBB();
    270     return false;
    271   }
    272 
    273   // If the block ends with two unconditional branches, handle it.  The second
    274   // one is not executed, so remove it.
    275   if (isUncondBranch(SecondLastInst) && isUncondBranch(LastInst)) {
    276     TBB = SecondLastInst->getOperand(0).getMBB();
    277     I = LastInst;
    278     if (AllowModify)
    279       I->eraseFromParent();
    280     return false;
    281   }
    282 
    283   // Otherwise, can't handle this.
    284   return true;
    285 }
    286 
    287 // search MBB for branch hint labels and branch hit ops
    288 static void removeHBR( MachineBasicBlock &MBB) {
    289   for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ++I){
    290     if (I->getOpcode() == SPU::HBRA ||
    291         I->getOpcode() == SPU::HBR_LABEL){
    292       I=MBB.erase(I);
    293       if (I == MBB.end())
    294         break;
    295     }
    296   }
    297 }
    298 
    299 unsigned
    300 SPUInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
    301   MachineBasicBlock::iterator I = MBB.end();
    302   removeHBR(MBB);
    303   if (I == MBB.begin())
    304     return 0;
    305   --I;
    306   while (I->isDebugValue()) {
    307     if (I == MBB.begin())
    308       return 0;
    309     --I;
    310   }
    311   if (!isCondBranch(I) && !isUncondBranch(I))
    312     return 0;
    313 
    314   // Remove the first branch.
    315   DEBUG(errs() << "Removing branch:                ");
    316   DEBUG(I->dump());
    317   I->eraseFromParent();
    318   I = MBB.end();
    319   if (I == MBB.begin())
    320     return 1;
    321 
    322   --I;
    323   if (!(isCondBranch(I) || isUncondBranch(I)))
    324     return 1;
    325 
    326   // Remove the second branch.
    327   DEBUG(errs() << "Removing second branch:         ");
    328   DEBUG(I->dump());
    329   I->eraseFromParent();
    330   return 2;
    331 }
    332 
    333 /** Find the optimal position for a hint branch instruction in a basic block.
    334  * This should take into account:
    335  *   -the branch hint delays
    336  *   -congestion of the memory bus
    337  *   -dual-issue scheduling (i.e. avoid insertion of nops)
    338  * Current implementation is rather simplistic.
    339  */
    340 static MachineBasicBlock::iterator findHBRPosition(MachineBasicBlock &MBB)
    341 {
    342    MachineBasicBlock::iterator J = MBB.end();
    343 	for( int i=0; i<8; i++) {
    344 		if( J == MBB.begin() ) return J;
    345 		J--;
    346 	}
    347 	return J;
    348 }
    349 
    350 unsigned
    351 SPUInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
    352                            MachineBasicBlock *FBB,
    353                            const SmallVectorImpl<MachineOperand> &Cond,
    354                            DebugLoc DL) const {
    355   // Shouldn't be a fall through.
    356   assert(TBB && "InsertBranch must not be told to insert a fallthrough");
    357   assert((Cond.size() == 2 || Cond.size() == 0) &&
    358          "SPU branch conditions have two components!");
    359 
    360   MachineInstrBuilder MIB;
    361   //TODO: make a more accurate algorithm.
    362   bool haveHBR = MBB.size()>8;
    363 
    364   removeHBR(MBB);
    365   MCSymbol *branchLabel = MBB.getParent()->getContext().CreateTempSymbol();
    366   // Add a label just before the branch
    367   if (haveHBR)
    368     MIB = BuildMI(&MBB, DL, get(SPU::HBR_LABEL)).addSym(branchLabel);
    369 
    370   // One-way branch.
    371   if (FBB == 0) {
    372     if (Cond.empty()) {
    373       // Unconditional branch
    374       MIB = BuildMI(&MBB, DL, get(SPU::BR));
    375       MIB.addMBB(TBB);
    376 
    377       DEBUG(errs() << "Inserted one-way uncond branch: ");
    378       DEBUG((*MIB).dump());
    379 
    380       // basic blocks have just one branch so it is safe to add the hint a its
    381       if (haveHBR) {
    382         MIB = BuildMI( MBB, findHBRPosition(MBB), DL, get(SPU::HBRA));
    383         MIB.addSym(branchLabel);
    384         MIB.addMBB(TBB);
    385       }
    386     } else {
    387       // Conditional branch
    388       MIB = BuildMI(&MBB, DL, get(Cond[0].getImm()));
    389       MIB.addReg(Cond[1].getReg()).addMBB(TBB);
    390 
    391       if (haveHBR) {
    392         MIB = BuildMI(MBB, findHBRPosition(MBB), DL, get(SPU::HBRA));
    393         MIB.addSym(branchLabel);
    394         MIB.addMBB(TBB);
    395       }
    396 
    397       DEBUG(errs() << "Inserted one-way cond branch:   ");
    398       DEBUG((*MIB).dump());
    399     }
    400     return 1;
    401   } else {
    402     MIB = BuildMI(&MBB, DL, get(Cond[0].getImm()));
    403     MachineInstrBuilder MIB2 = BuildMI(&MBB, DL, get(SPU::BR));
    404 
    405     // Two-way Conditional Branch.
    406     MIB.addReg(Cond[1].getReg()).addMBB(TBB);
    407     MIB2.addMBB(FBB);
    408 
    409     if (haveHBR) {
    410       MIB = BuildMI( MBB, findHBRPosition(MBB), DL, get(SPU::HBRA));
    411       MIB.addSym(branchLabel);
    412       MIB.addMBB(FBB);
    413     }
    414 
    415     DEBUG(errs() << "Inserted conditional branch:    ");
    416     DEBUG((*MIB).dump());
    417     DEBUG(errs() << "part 2: ");
    418     DEBUG((*MIB2).dump());
    419    return 2;
    420   }
    421 }
    422 
    423 //! Reverses a branch's condition, returning false on success.
    424 bool
    425 SPUInstrInfo::ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond)
    426   const {
    427   // Pretty brainless way of inverting the condition, but it works, considering
    428   // there are only two conditions...
    429   static struct {
    430     unsigned Opc;               //! The incoming opcode
    431     unsigned RevCondOpc;        //! The reversed condition opcode
    432   } revconds[] = {
    433     { SPU::BRNZr32, SPU::BRZr32 },
    434     { SPU::BRNZv4i32, SPU::BRZv4i32 },
    435     { SPU::BRZr32, SPU::BRNZr32 },
    436     { SPU::BRZv4i32, SPU::BRNZv4i32 },
    437     { SPU::BRHNZr16, SPU::BRHZr16 },
    438     { SPU::BRHNZv8i16, SPU::BRHZv8i16 },
    439     { SPU::BRHZr16, SPU::BRHNZr16 },
    440     { SPU::BRHZv8i16, SPU::BRHNZv8i16 }
    441   };
    442 
    443   unsigned Opc = unsigned(Cond[0].getImm());
    444   // Pretty dull mapping between the two conditions that SPU can generate:
    445   for (int i = sizeof(revconds)/sizeof(revconds[0]) - 1; i >= 0; --i) {
    446     if (revconds[i].Opc == Opc) {
    447       Cond[0].setImm(revconds[i].RevCondOpc);
    448       return false;
    449     }
    450   }
    451 
    452   return true;
    453 }
    454