| /external/llvm/lib/CodeGen/ |
| RegisterCoalescer.h | 36 /// SrcReg - the virtual register that will be coalesced into dstReg.
37 unsigned SrcReg;
39 /// subReg_ - The subregister index of srcReg in DstReg. It is possible the
40 /// coalesce SrcReg into a subreg of the larger DstReg when DstReg is a
50 /// Flipped - True when DstReg and SrcReg are reversed from the oriignal
60 : TII(tii), TRI(tri), DstReg(0), SrcReg(0), SubIdx(0),
67 /// flip - Swap SrcReg and DstReg. Return false if swapping is impossible
95 unsigned getSrcReg() const { return SrcReg; }
97 /// getSubIdx - Return the subregister index in DstReg that SrcReg will be
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| OptimizePHIs.cpp | 100 unsigned SrcReg = MI->getOperand(i).getReg();
101 if (SrcReg == DstReg)
103 MachineInstr *SrcMI = MRI->getVRegDef(SrcReg);
121 SingleValReg = SrcReg;
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| MachineSSAUpdater.cpp | 94 unsigned SrcReg = I->getOperand(i).getReg();
96 if (AVals[SrcBB] != SrcReg) {
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| MachineSink.cpp | 114 unsigned SrcReg = MI->getOperand(1).getReg();
116 if (!TargetRegisterInfo::isVirtualRegister(SrcReg) ||
118 !MRI->hasOneNonDBGUse(SrcReg))
121 const TargetRegisterClass *SRC = MRI->getRegClass(SrcReg);
126 MachineInstr *DefMI = MRI->getVRegDef(SrcReg);
131 MRI->replaceRegWith(DstReg, SrcReg);
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| PHIElimination.cpp | 175 unsigned SrcReg = MPhi->getOperand(i).getReg();
176 const MachineInstr *DefMI = MRI->getVRegDef(SrcReg);
285 unsigned SrcReg = MPhi->getOperand(i*2+1).getReg();
288 assert(TargetRegisterInfo::isVirtualRegister(SrcReg) &&
297 MachineInstr *DefMI = MRI->getVRegDef(SrcReg);
312 findPHICopyInsertPoint(&opBlock, &MBB, SrcReg);
317 TII->get(TargetOpcode::COPY), IncomingReg).addReg(SrcReg, 0, SrcSubReg);
334 bool ValueIsUsed = VRegPHIUseCount[BBVRegPair(opBlock.getNumber(), SrcReg)];
338 if (!ValueIsUsed && !LV->isLiveOut(SrcReg, opBlock)) {
346 if (Term != opBlock.end() && Term->readsRegister(SrcReg)) {
[all...] |
| PeepholeOptimizer.cpp | 134 unsigned SrcReg, DstReg, SubIdx;
135 if (!TII->isCoalescableExtInstr(*MI, SrcReg, DstReg, SubIdx))
139 TargetRegisterInfo::isPhysicalRegister(SrcReg))
142 MachineRegisterInfo::use_nodbg_iterator UI = MRI->use_nodbg_begin(SrcReg);
162 UI = MRI->use_nodbg_begin(SrcReg);
235 const TargetRegisterClass *RC = MRI->getRegClass(SrcReg);
337 unsigned SrcReg;
339 if (!TII->AnalyzeCompare(MI, SrcReg, CmpMask, CmpValue) ||
340 TargetRegisterInfo::isPhysicalRegister(SrcReg))
344 if (TII->OptimizeCompareInstr(MI, SrcReg, CmpMask, CmpValue, MRI))
[all...] |
| MachineCSE.cpp | 130 unsigned SrcReg = DefMI->getOperand(1).getReg();
131 if (!TargetRegisterInfo::isVirtualRegister(SrcReg))
135 if (!MRI->constrainRegClass(SrcReg, MRI->getRegClass(Reg)))
139 MO.setReg(SrcReg);
140 MRI->clearKillFlags(SrcReg);
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| StrongPHIElimination.cpp | 250 unsigned SrcReg = SrcMO.getReg();
251 addReg(SrcReg);
252 unionRegs(DestReg, SrcReg);
254 MachineInstr *DefMI = MRI->getVRegDef(SrcReg);
292 unsigned SrcReg = BBI->getOperand(i).getReg();
293 addReg(SrcReg);
294 unionRegs(DestReg, SrcReg);
309 unsigned SrcReg = PHI->getOperand(1).getReg();
310 unsigned SrcColor = getRegColor(SrcReg);
313 NewReg = SrcReg;
[all...] |
| TailDuplication.cpp | 238 unsigned SrcReg = LI->second[j].second;
239 SSAUpdate.AddAvailableValue(SrcBB, SrcReg);
351 unsigned SrcReg = MI.getOperand(i).getReg();
352 UsedByPhi->insert(SrcReg);
385 unsigned SrcReg = MI->getOperand(SrcOpIdx).getReg();
387 LocalVRMap.insert(std::make_pair(DefReg, SrcReg));
392 Copies.push_back(std::make_pair(NewDef, SrcReg));
493 unsigned SrcReg = LI->second[j].second;
495 II->getOperand(Idx).setReg(SrcReg);
499 II->addOperand(MachineOperand::CreateReg(SrcReg, false))
[all...] |
| RegAllocLinearScan.cpp | 466 // Defined by a copy, try to extend SrcReg forward
[all...] |
| TwoAddressInstructionPass.cpp | 393 unsigned &SrcReg, unsigned &DstReg,
395 SrcReg = 0;
399 SrcReg = MI.getOperand(1).getReg();
402 SrcReg = MI.getOperand(2).getReg();
406 IsSrcPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg);
442 unsigned SrcReg, DstReg;
445 if (!isCopyToReg(*DefMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys))
447 Reg = SrcReg;
484 unsigned SrcReg;
486 if (isCopyToReg(UseMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys))
[all...] |
| RegisterCoalescer.cpp | 113 /// JoinCopy - Attempt to join intervals corresponding to SrcReg/DstReg,
154 bool isWinToJoinCrossClass(unsigned SrcReg,
160 /// UpdateRegDefsUses - Replace all defs and uses of SrcReg to DstReg and
243 SrcReg = DstReg = SubIdx = 0;
320 SrcReg = Src;
329 std::swap(SrcReg, DstReg);
341 // Find the virtual register that is SrcReg.
342 if (Dst == SrcReg) {
345 } else if (Src != SrcReg) {
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsExpandPseudo.cpp | 104 unsigned SrcReg = I->getOperand(1).getReg();
108 const unsigned* SubReg = TM.getRegisterInfo()->getSubRegisters(SrcReg);
|
| MipsISelDAGToDAG.cpp | 313 unsigned SrcReg = Mips::HWR29;
316 Node->getValueType(0), CurDAG->getRegister(SrcReg, MVT::i32));
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| FunctionLoweringInfo.cpp | 301 unsigned SrcReg = ValueMap[V];
302 if (!TargetRegisterInfo::isVirtualRegister(SrcReg)) {
306 const LiveOutInfo *SrcLOI = GetLiveOutRegInfo(SrcReg, BitWidth);
338 unsigned SrcReg = ValueMap[V];
339 if (!TargetRegisterInfo::isVirtualRegister(SrcReg)) {
343 const LiveOutInfo *SrcLOI = GetLiveOutRegInfo(SrcReg, BitWidth);
|
| /external/llvm/lib/Target/ARM/ |
| Thumb2ITBlockPass.cpp | 121 unsigned SrcReg = MI->getOperand(1).getReg();
124 if (Uses.count(DstReg) || Defs.count(SrcReg))
|
| ARMExpandPseudoInsts.cpp | 495 unsigned SrcReg = MI.getOperand(OpIdx++).getReg();
497 GetDSubRegs(SrcReg, RegSpc, TRI, D0, D1, D2, D3);
509 MIB->addRegisterKilled(SrcReg, TRI, true);
621 unsigned SrcReg = MI.getOperand(OpIdx++).getReg();
623 GetDSubRegs(SrcReg, SingleSpc, TRI, D0, D1, D2, D3);
638 MIB->addRegisterKilled(SrcReg, TRI, true);
[all...] |
| ARMAsmPrinter.cpp | [all...] |
| ARMFastISel.cpp | 177 bool ARMEmitStore(EVT VT, unsigned SrcReg, Address &Addr);
183 unsigned ARMMoveToFPReg(EVT VT, unsigned SrcReg);
184 unsigned ARMMoveToIntReg(EVT VT, unsigned SrcReg);
475 unsigned ARMFastISel::ARMMoveToFPReg(EVT VT, unsigned SrcReg) {
481 .addReg(SrcReg));
485 unsigned ARMFastISel::ARMMoveToIntReg(EVT VT, unsigned SrcReg) {
491 .addReg(SrcReg));
[all...] |
| ARMISelDAGToDAG.cpp | [all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCRegisterInfo.cpp | 458 MachineInstr &MI = *II; // ; SPILL_CR <SrcReg>, <offset>, <FI>
467 unsigned SrcReg = MI.getOperand(0).getReg();
471 // an MFCRpsued to save all of the CRBits and, if needed, kill the SrcReg.
473 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill()));
477 if (SrcReg != PPC::CR0)
481 .addImm(getPPCRegisterNumbering(SrcReg) * 4)
|
| PPCFrameLowering.cpp | 131 unsigned SrcReg = MI->getOperand(1).getReg();
135 if (DstReg != SrcReg)
137 .addReg(SrcReg)
141 .addReg(SrcReg, RegState::Kill)
144 if (DstReg != SrcReg)
146 .addReg(SrcReg)
150 .addReg(SrcReg, RegState::Kill)
153 if (DstReg != SrcReg)
155 .addReg(SrcReg)
159 .addReg(SrcReg, RegState::Kill
[all...] |
| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| X86MCCodeEmitter.cpp | 64 unsigned SrcReg = MI.getOperand(OpNum).getReg();
66 if (X86II::isX86_64ExtendedReg(SrcReg))
492 unsigned SrcReg = MI.getOperand(i).getReg();
493 if (SrcReg >= X86::YMM0 && SrcReg <= X86::YMM15)
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/X86/ |
| X86FastISel.cpp | 772 unsigned SrcReg = Reg + VA.getValNo();
788 SrcReg = FastEmitZExtFromI1(MVT::i8, SrcReg, /*TODO: Kill=*/false);
793 SrcReg = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Op,
794 SrcReg, /*TODO: Kill=*/false);
799 const TargetRegisterClass* SrcRC = MRI.getRegClass(SrcReg);
804 DstReg).addReg(SrcReg);
[all...] |
