| /external/llvm/lib/CodeGen/ |
| AllocationOrder.cpp | 29 const TargetRegisterClass *RC = VRM.getRegInfo().getRegClass(VirtReg);
45 TRI.getRawAllocationOrder(RC, HintPair.first, Hint,
65 ArrayRef<unsigned> O = RCI.getOrder(RC);
72 !RC->contains(Hint) || RCI.isReserved(Hint)))
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| LiveStackAnalysis.cpp | 55 LiveStacks::getOrCreateInterval(int Slot, const TargetRegisterClass *RC) {
61 S2RCMap.insert(std::make_pair(Slot, RC));
65 S2RCMap[Slot] = TRI->getCommonSubClass(OldRC, RC);
77 const TargetRegisterClass *RC = getIntervalRegClass(Slot);
78 if (RC)
79 OS << " [" << RC->getName() << "]\n";
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| AggressiveAntiDepBreaker.h | 44 /// RC - The register class
45 const TargetRegisterClass *RC;
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| ExecutionDepsFix.cpp | 110 const TargetRegisterClass *const RC;
123 ExeDepsFix(const TargetRegisterClass *rc)
124 : MachineFunctionPass(ID), RC(rc), NumRegs(RC->getNumRegs()) {}
457 assert(NumRegs == RC->getNumRegs() && "Bad regclass");
462 for (TargetRegisterClass::const_iterator I = RC->begin(), E = RC->end();
472 // Given a PhysReg, AliasMap[PhysReg] is either the relevant index into RC,
475 for (unsigned i = 0, e = RC->getNumRegs(); i != e; ++i
[all...] |
| LocalStackSlotAllocation.cpp | 321 const TargetRegisterClass *RC = TRI->getPointerRegClass();
322 BaseReg = Fn.getRegInfo().createVirtualRegister(RC);
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| ProcessImplicitDefs.cpp | 276 const TargetRegisterClass* RC = MRI->getRegClass(Reg);
277 unsigned NewVReg = MRI->createVirtualRegister(RC);
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| VirtRegMap.cpp | 103 unsigned VirtRegMap::createSpillSlot(const TargetRegisterClass *RC) {
104 int SS = MF->getFrameInfo()->CreateSpillStackObject(RC->getSize(),
105 RC->getAlignment());
133 const TargetRegisterClass* RC = MF->getRegInfo().getRegClass(virtReg);
134 return Virt2StackSlotMap[virtReg] = createSpillSlot(RC);
162 int VirtRegMap::getEmergencySpillSlot(const TargetRegisterClass *RC) {
164 EmergencySpillSlots.find(RC);
167 return EmergencySpillSlots[RC] = createSpillSlot(RC);
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| CriticalAntiDepBreaker.cpp | 386 const TargetRegisterClass *RC)
388 ArrayRef<unsigned> Order = RegClassInfo.getOrder(RC);
597 const TargetRegisterClass *RC = AntiDepReg != 0 ? Classes[AntiDepReg] : 0;
598 assert((AntiDepReg == 0 || RC != NULL) &&
600 if (RC == reinterpret_cast<TargetRegisterClass *>(-1))
614 RC)) {
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| PHIElimination.cpp | 227 const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(DestReg);
228 entry = IncomingReg = MF.getRegInfo().createVirtualRegister(RC);
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| PeepholeOptimizer.cpp | 235 const TargetRegisterClass *RC = MRI->getRegClass(SrcReg);
243 unsigned NewVR = MRI->createVirtualRegister(RC);
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| Spiller.cpp | 222 const TargetRegisterClass *RC = mf->getRegInfo().getRegClass(LRE.getReg());
223 LiveInterval &SI = lss->getOrCreateInterval(SS, RC);
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| TargetInstrInfoImpl.cpp | 248 const TargetRegisterClass *RC = MRI.getRegClass(FoldReg);
251 return RC->contains(LiveOp.getReg()) ? RC : 0;
253 if (RC->hasSubClassEq(MRI.getRegClass(LiveReg)))
254 return RC;
313 const TargetRegisterClass *RC = canFoldCopy(MI, Ops[0]);
314 if (!RC)
322 storeRegToStackSlot(*MBB, Pos, MO.getReg(), MO.isKill(), FI, RC, TRI);
324 loadRegFromStackSlot(*MBB, Pos, MO.getReg(), FI, RC, TRI);
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| VirtRegRewriter.cpp | 417 unsigned GetRegForReload(const TargetRegisterClass *RC, unsigned PhysReg,
445 const TargetRegisterClass* RC = MF.getRegInfo().getRegClass(VirtReg);
446 return GetRegForReload(RC, PhysReg, MF, MI, Spills, MaybeDeadStores,
705 static unsigned findSuperReg(const TargetRegisterClass *RC, unsigned SubReg,
707 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
787 const TargetRegisterClass* RC = TRI->getMinimalPhysRegClass(Reg);
791 if (!TII->isSafeToMoveRegClassDefs(RC))
[all...] |
| /external/llvm/lib/Target/Blackfin/ |
| BlackfinFrameLowering.cpp | 122 const TargetRegisterClass *RC = BF::DPRegisterClass;
126 RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
127 RC->getAlignment(),
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| BlackfinISelLowering.cpp | 186 TargetRegisterClass *RC = VA.getLocReg() == BF::P0 ?
188 assert(RC->contains(VA.getLocReg()) && "Unexpected regclass in CCState");
189 assert(RC->hasType(RegVT) && "Unexpected regclass in CCState");
191 unsigned Reg = MF.getRegInfo().createVirtualRegister(RC);
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| /external/llvm/lib/Target/ |
| TargetRegisterInfo.cpp | 62 const TargetRegisterClass* RC = *I;
63 if ((VT == MVT::Other || RC->hasType(VT)) && RC->contains(reg) &&
64 (!BestRC || BestRC->hasSubClass(RC)))
65 BestRC = RC;
75 const TargetRegisterClass *RC, BitVector &R){
76 ArrayRef<unsigned> Order = RC->getRawAllocationOrder(MF);
82 const TargetRegisterClass *RC) const {
84 if (RC) {
85 getAllocatableSetForRC(MF, RC, Allocatable)
[all...] |
| /external/dropbear/libtomcrypt/src/ciphers/ |
| noekeon.c | 33 static const ulong32 RC[] = {
129 a ^= RC[i]; \
141 a ^= RC[16];
185 a ^= RC[i]; \
197 a ^= RC[0];
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| /external/llvm/lib/Target/CellSPU/ |
| SPUFrameLowering.cpp | 251 const TargetRegisterClass *RC = &SPU::R32CRegClass;
252 RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
253 RC->getAlignment(),
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| /external/llvm/utils/TableGen/ |
| FastISelEmitter.cpp | 36 const CodeGenRegisterClass *RC;
250 const CodeGenRegisterClass *RC = 0;
254 RC = &Target.getRegisterClass(OpLeafRec);
256 RC = Target.getRegBank().getRegClassForRegister(OpLeafRec);
261 if (!RC)
267 if (DstRC != RC && !DstRC->hasSubClass(RC))
270 DstRC = RC;
643 OS << InstNS << Memo.RC->getName() << "RegisterClass";
735 OS << InstNS << Memo.RC->getName() << "RegisterClass"
[all...] |
| CodeGenTarget.cpp | 189 const CodeGenRegisterClass &RC = *RCs[i];
190 if (RC.contains(Reg)) {
191 const std::vector<MVT::SimpleValueType> &InVTs = RC.getValueTypes();
346 std::vector<CodeGenIntrinsic> llvm::LoadIntrinsics(const RecordKeeper &RC,
348 std::vector<Record*> I = RC.getAllDerivedDefinitions("Intrinsic");
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| RegisterInfoEmitter.cpp | 339 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
340 const CodeGenRegisterClass &RC = *RegisterClasses[rc];
341 ArrayRef<Record*> Order = RC.getOrder();
344 std::string Name = RC.getName();
372 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| InstrEmitter.cpp | 116 const TargetRegisterClass *RC = 0;
118 RC = TII->getRegClass(II, i+II.getNumDefs(), TRI);
120 UseRC = RC;
121 else if (RC) {
123 TRI->getCommonSubClass(UseRC, RC);
199 const TargetRegisterClass *RC = TII->getRegClass(II, i, TRI);
218 if (RegRC == RC) {
230 assert(RC && "Isn't a register operand!");
231 VRBase = MRI->createVirtualRegister(RC);
255 const TargetRegisterClass *RC = TLI->getRegClassFor(Op.getValueType())
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCRegisterInfo.cpp | 322 const TargetRegisterClass *RC, int SPAdj) {
324 unsigned Reg = RS->FindUnusedReg(RC);
328 Reg = RS->scavengeRegister(RC, II, SPAdj);
372 const TargetRegisterClass *RC = LP64 ? G8RC : GPRC;
377 Reg = findScratchRegister(II, RS, RC, SPAdj);
465 const TargetRegisterClass *RC = Subtarget.isPPC64() ? G8RC : GPRC;
466 unsigned Reg = findScratchRegister(II, RS, RC, SPAdj);
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| /external/llvm/lib/Target/XCore/ |
| XCoreFrameLowering.cpp | 296 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
298 it->getFrameIdx(), RC, TRI);
322 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
324 RC, TRI);
345 const TargetRegisterClass *RC = XCore::GRRegsRegisterClass;
354 FrameIdx = MFI->CreateFixedObject(RC->getSize(), 0, true);
356 FrameIdx = MFI->CreateStackObject(RC->getSize(), RC->getAlignment(),
364 RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
365 RC->getAlignment()
[all...] |
| /external/clang/test/SemaCXX/ |
| nested-name-spec.cpp | 71 struct RC;
77 struct A2::RC {
101 void f6(int A2::RC::x); // expected-error{{parameter declarator cannot be qualified}}
103 int A2::RC::x; // expected-error{{non-static data member defined out-of-line}}
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