1 //===-- llvm/CodeGen/AllocationOrder.cpp - Allocation Order ---------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements an allocation order for virtual registers. 11 // 12 // The preferred allocation order for a virtual register depends on allocation 13 // hints and target hooks. The AllocationOrder class encapsulates all of that. 14 // 15 //===----------------------------------------------------------------------===// 16 17 #include "AllocationOrder.h" 18 #include "RegisterClassInfo.h" 19 #include "VirtRegMap.h" 20 #include "llvm/CodeGen/MachineRegisterInfo.h" 21 22 using namespace llvm; 23 24 // Compare VirtRegMap::getRegAllocPref(). 25 AllocationOrder::AllocationOrder(unsigned VirtReg, 26 const VirtRegMap &VRM, 27 const RegisterClassInfo &RegClassInfo) 28 : Begin(0), End(0), Pos(0), RCI(RegClassInfo), OwnedBegin(false) { 29 const TargetRegisterClass *RC = VRM.getRegInfo().getRegClass(VirtReg); 30 std::pair<unsigned, unsigned> HintPair = 31 VRM.getRegInfo().getRegAllocationHint(VirtReg); 32 33 // HintPair.second is a register, phys or virt. 34 Hint = HintPair.second; 35 36 // Translate to physreg, or 0 if not assigned yet. 37 if (TargetRegisterInfo::isVirtualRegister(Hint)) 38 Hint = VRM.getPhys(Hint); 39 40 // The first hint pair component indicates a target-specific hint. 41 if (HintPair.first) { 42 const TargetRegisterInfo &TRI = VRM.getTargetRegInfo(); 43 // The remaining allocation order may depend on the hint. 44 ArrayRef<unsigned> Order = 45 TRI.getRawAllocationOrder(RC, HintPair.first, Hint, 46 VRM.getMachineFunction()); 47 if (Order.empty()) 48 return; 49 50 // Copy the allocation order with reserved registers removed. 51 OwnedBegin = true; 52 unsigned *P = new unsigned[Order.size()]; 53 Begin = P; 54 for (unsigned i = 0; i != Order.size(); ++i) 55 if (!RCI.isReserved(Order[i])) 56 *P++ = Order[i]; 57 End = P; 58 59 // Target-dependent hints require resolution. 60 Hint = TRI.ResolveRegAllocHint(HintPair.first, Hint, 61 VRM.getMachineFunction()); 62 } else { 63 // If there is no hint or just a normal hint, use the cached allocation 64 // order from RegisterClassInfo. 65 ArrayRef<unsigned> O = RCI.getOrder(RC); 66 Begin = O.begin(); 67 End = O.end(); 68 } 69 70 // The hint must be a valid physreg for allocation. 71 if (Hint && (!TargetRegisterInfo::isPhysicalRegister(Hint) || 72 !RC->contains(Hint) || RCI.isReserved(Hint))) 73 Hint = 0; 74 } 75 76 AllocationOrder::~AllocationOrder() { 77 if (OwnedBegin) 78 delete [] Begin; 79 } 80
