| /external/llvm/lib/CodeGen/ |
| RegisterClassInfo.h | 60 // Compute all information about RC.
61 void compute(const TargetRegisterClass *RC) const;
63 // Return an up-to-date RCInfo for RC.
64 const RCInfo &get(const TargetRegisterClass *RC) const {
65 const RCInfo &RCI = RegClass[RC->getID()];
67 compute(RC);
79 /// registers in RC in the current function.
80 unsigned getNumAllocatableRegs(const TargetRegisterClass *RC) const {
81 return get(RC).NumRegs;
84 /// getOrder - Returns the preferred allocation order for RC. The orde
[all...] |
| LiveStackAnalysis.cpp | 55 LiveStacks::getOrCreateInterval(int Slot, const TargetRegisterClass *RC) {
61 S2RCMap.insert(std::make_pair(Slot, RC));
65 S2RCMap[Slot] = TRI->getCommonSubClass(OldRC, RC);
77 const TargetRegisterClass *RC = getIntervalRegClass(Slot);
78 if (RC)
79 OS << " [" << RC->getName() << "]\n";
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| AllocationOrder.cpp | 29 const TargetRegisterClass *RC = VRM.getRegInfo().getRegClass(VirtReg);
45 TRI.getRawAllocationOrder(RC, HintPair.first, Hint,
65 ArrayRef<unsigned> O = RCI.getOrder(RC);
72 !RC->contains(Hint) || RCI.isReserved(Hint)))
|
| RegisterClassInfo.cpp | 67 /// compute - Compute the preferred allocation order for RC with reserved
70 void RegisterClassInfo::compute(const TargetRegisterClass *RC) const {
71 RCInfo &RCI = RegClass[RC->getID()];
74 unsigned NumRegs = RC->getNumRegs();
84 ArrayRef<unsigned> RawOrder = RC->getRawAllocationOrder(*MF);
102 // Check if RC is a proper sub-class.
103 if (const TargetRegisterClass *Super = TRI->getLargestLegalSuperClass(RC))
104 if (Super != RC && getNumAllocatableRegs(Super) > RCI.NumRegs)
108 dbgs() << "AllocationOrder(" << RC->getName() << ") = [";
|
| RegisterScavenging.cpp | 238 unsigned RegScavenger::FindUnusedReg(const TargetRegisterClass *RC) const {
239 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
251 BitVector RegScavenger::getRegsAvailable(const TargetRegisterClass *RC) {
253 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
330 unsigned RegScavenger::scavengeRegister(const TargetRegisterClass *RC,
335 TRI->getAllocatableSet(*I->getParent()->getParent(), RC);
349 BitVector Available = getRegsAvailable(RC);
372 if (!TRI->saveScavengerRegister(*MBB, I, UseMI, RC, SReg))
[all...] |
| /external/llvm/lib/Target/ |
| TargetRegisterInfo.cpp | 62 const TargetRegisterClass* RC = *I;
63 if ((VT == MVT::Other || RC->hasType(VT)) && RC->contains(reg) &&
64 (!BestRC || BestRC->hasSubClass(RC)))
65 BestRC = RC;
75 const TargetRegisterClass *RC, BitVector &R){
76 ArrayRef<unsigned> Order = RC->getRawAllocationOrder(MF);
82 const TargetRegisterClass *RC) const {
84 if (RC) {
85 getAllocatableSetForRC(MF, RC, Allocatable)
[all...] |
| /external/llvm/utils/release/ |
| test-release.sh | 28 RC=""
39 echo "usage: `basename $0` -release X.Y -rc NUM [OPTIONS]"
42 echo " -rc NUM The pre-release candidate number."
61 -rc | --rc | -RC | --RC )
63 RC=$1
115 if [ -z "$RC" ]; then
135 BuildDir=$BuildDir/rc$R
[all...] |
| /external/llvm/lib/Target/ARM/ |
| Thumb1InstrInfo.h | 47 const TargetRegisterClass *RC,
53 const TargetRegisterClass *RC,
|
| Thumb1InstrInfo.cpp | 48 const TargetRegisterClass *RC,
50 assert((RC == ARM::tGPRRegisterClass ||
54 if (RC == ARM::tGPRRegisterClass ||
77 const TargetRegisterClass *RC,
79 assert((RC == ARM::tGPRRegisterClass ||
83 if (RC == ARM::tGPRRegisterClass ||
|
| Thumb2InstrInfo.h | 49 const TargetRegisterClass *RC,
55 const TargetRegisterClass *RC,
|
| ARMBaseRegisterInfo.h | 114 virtual bool canCombineSubRegIndices(const TargetRegisterClass *RC,
120 getCrossCopyRegClass(const TargetRegisterClass *RC) const;
123 getLargestLegalSuperClass(const TargetRegisterClass *RC) const;
125 unsigned getRegPressureLimit(const TargetRegisterClass *RC,
128 ArrayRef<unsigned> getRawAllocationOrder(const TargetRegisterClass *RC,
138 virtual bool avoidWriteAfterWrite(const TargetRegisterClass *RC) const;
|
| Thumb1RegisterInfo.h | 32 getLargestLegalSuperClass(const TargetRegisterClass *RC) const;
62 const TargetRegisterClass *RC,
|
| /external/llvm/include/llvm/Target/ |
| TargetRegisterInfo.h | 142 bool hasSubClass(const TargetRegisterClass *RC) const {
143 return RC != this && hasSubClassEq(RC);
146 /// hasSubClassEq - Returns true if RC is a sub-class of or equal to this
148 bool hasSubClassEq(const TargetRegisterClass *RC) const {
149 unsigned ID = RC->getID();
155 bool hasSuperClass(const TargetRegisterClass *RC) const {
156 return RC->hasSubClass(this);
159 /// hasSuperClassEq - Returns true if RC is a super-class of or equal to this
161 bool hasSuperClassEq(const TargetRegisterClass *RC) const
[all...] |
| /external/llvm/lib/Target/Blackfin/ |
| BlackfinInstrInfo.h | 58 const TargetRegisterClass *RC,
64 const TargetRegisterClass *RC,
70 const TargetRegisterClass *RC,
75 const TargetRegisterClass *RC,
|
| BlackfinInstrInfo.cpp | 162 const TargetRegisterClass *RC) {
166 return Test.hasSubClassEq(RC);
175 const TargetRegisterClass *RC,
179 if (inClass(BF::DPRegClass, SrcReg, RC)) {
187 if (inClass(BF::D16RegClass, SrcReg, RC)) {
195 if (inClass(BF::AnyCCRegClass, SrcReg, RC)) {
204 RC->getName()).c_str());
212 const TargetRegisterClass *RC,
222 const TargetRegisterClass *RC,
225 if (inClass(BF::DPRegClass, DestReg, RC)) {
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86RegisterInfo.h | 78 getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const;
81 getLargestLegalSuperClass(const TargetRegisterClass *RC) const;
91 getCrossCopyRegClass(const TargetRegisterClass *RC) const;
93 unsigned getRegPressureLimit(const TargetRegisterClass *RC,
|
| /external/llvm/utils/TableGen/ |
| RegisterInfoEmitter.cpp | 339 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
340 const CodeGenRegisterClass &RC = *RegisterClasses[rc];
341 ArrayRef<Record*> Order = RC.getOrder();
344 std::string Name = RC.getName();
372 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
[all...] |
| CodeGenRegisters.cpp | 302 // SubRegClasses is a list<dag> containing (RC, subregindex, ...) dags.
401 // Returns true if RC is a strict subclass.
402 // RC is a sub-class of this class if it is a valid replacement for any
406 // 1. All RC registers are also in this.
407 // 2. The RC spill size must not be smaller than our spill size.
408 // 3. RC spill alignment must be compatible with ours.
468 CodeGenRegisterClass &RC = *RegClasses[rci - 1];
469 RC.SubClasses.resize(RegClasses.size());
470 RC.SubClasses.set(RC.EnumValue)
[all...] |
| /external/llvm/lib/Target/CellSPU/ |
| SPURegisterInfo.h | 54 virtual unsigned getRegPressureLimit( const TargetRegisterClass *RC,
95 const TargetRegisterClass *RC,
|
| SPUInstrInfo.cpp | 142 const TargetRegisterClass *RC,
147 if (RC == SPU::GPRCRegisterClass) {
149 } else if (RC == SPU::R64CRegisterClass) {
151 } else if (RC == SPU::R64FPRegisterClass) {
153 } else if (RC == SPU::R32CRegisterClass) {
155 } else if (RC == SPU::R32FPRegisterClass) {
157 } else if (RC == SPU::R16CRegisterClass) {
159 } else if (RC == SPU::R8CRegisterClass) {
161 } else if (RC == SPU::VECREGRegisterClass) {
177 const TargetRegisterClass *RC,
[all...] |
| SPUInstrInfo.h | 56 const TargetRegisterClass *RC,
63 const TargetRegisterClass *RC,
|
| /external/llvm/include/llvm/CodeGen/ |
| FastISel.h | 240 const TargetRegisterClass *RC);
246 const TargetRegisterClass *RC,
253 const TargetRegisterClass *RC,
261 const TargetRegisterClass *RC,
270 const TargetRegisterClass *RC,
278 const TargetRegisterClass *RC,
286 const TargetRegisterClass *RC,
294 const TargetRegisterClass *RC,
302 const TargetRegisterClass *RC,
307 const TargetRegisterClass *RC,
[all...] |
| /external/llvm/include/llvm/ |
| InlineAsm.h | 241 static unsigned getFlagWordForRegClass(unsigned InputFlag, unsigned RC) {
242 // Store RC + 1, reserve the value 0 to mean 'no register class'.
243 ++RC;
244 assert(RC <= 0x7fff && "Too large register class ID");
246 return InputFlag | (RC << 16);
279 /// class constraint. Sets RC to the register class ID.
280 static bool hasRegClassConstraint(unsigned Flag, unsigned &RC) {
285 // stores RC + 1.
288 RC = High - 1;
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCInstrInfo.h | 73 const TargetRegisterClass *RC,
77 const TargetRegisterClass *RC,
123 const TargetRegisterClass *RC,
129 const TargetRegisterClass *RC,
|
| /external/llvm/lib/Target/Alpha/ |
| AlphaInstrInfo.h | 52 const TargetRegisterClass *RC,
58 const TargetRegisterClass *RC,
|
