1 //===- Thumb2InstrInfo.cpp - Thumb-2 Instruction Information ----*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the Thumb-2 implementation of the TargetInstrInfo class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "Thumb2InstrInfo.h" 15 #include "ARM.h" 16 #include "ARMConstantPoolValue.h" 17 #include "ARMMachineFunctionInfo.h" 18 #include "Thumb2InstrInfo.h" 19 #include "MCTargetDesc/ARMAddressingModes.h" 20 #include "llvm/CodeGen/MachineFrameInfo.h" 21 #include "llvm/CodeGen/MachineInstrBuilder.h" 22 #include "llvm/CodeGen/MachineMemOperand.h" 23 #include "llvm/CodeGen/PseudoSourceValue.h" 24 #include "llvm/ADT/SmallVector.h" 25 #include "llvm/Support/CommandLine.h" 26 27 using namespace llvm; 28 29 static cl::opt<bool> 30 OldT2IfCvt("old-thumb2-ifcvt", cl::Hidden, 31 cl::desc("Use old-style Thumb2 if-conversion heuristics"), 32 cl::init(false)); 33 34 Thumb2InstrInfo::Thumb2InstrInfo(const ARMSubtarget &STI) 35 : ARMBaseInstrInfo(STI), RI(*this, STI) { 36 } 37 38 unsigned Thumb2InstrInfo::getUnindexedOpcode(unsigned Opc) const { 39 // FIXME 40 return 0; 41 } 42 43 void 44 Thumb2InstrInfo::ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail, 45 MachineBasicBlock *NewDest) const { 46 MachineBasicBlock *MBB = Tail->getParent(); 47 ARMFunctionInfo *AFI = MBB->getParent()->getInfo<ARMFunctionInfo>(); 48 if (!AFI->hasITBlocks()) { 49 TargetInstrInfoImpl::ReplaceTailWithBranchTo(Tail, NewDest); 50 return; 51 } 52 53 // If the first instruction of Tail is predicated, we may have to update 54 // the IT instruction. 55 unsigned PredReg = 0; 56 ARMCC::CondCodes CC = llvm::getInstrPredicate(Tail, PredReg); 57 MachineBasicBlock::iterator MBBI = Tail; 58 if (CC != ARMCC::AL) 59 // Expecting at least the t2IT instruction before it. 60 --MBBI; 61 62 // Actually replace the tail. 63 TargetInstrInfoImpl::ReplaceTailWithBranchTo(Tail, NewDest); 64 65 // Fix up IT. 66 if (CC != ARMCC::AL) { 67 MachineBasicBlock::iterator E = MBB->begin(); 68 unsigned Count = 4; // At most 4 instructions in an IT block. 69 while (Count && MBBI != E) { 70 if (MBBI->isDebugValue()) { 71 --MBBI; 72 continue; 73 } 74 if (MBBI->getOpcode() == ARM::t2IT) { 75 unsigned Mask = MBBI->getOperand(1).getImm(); 76 if (Count == 4) 77 MBBI->eraseFromParent(); 78 else { 79 unsigned MaskOn = 1 << Count; 80 unsigned MaskOff = ~(MaskOn - 1); 81 MBBI->getOperand(1).setImm((Mask & MaskOff) | MaskOn); 82 } 83 return; 84 } 85 --MBBI; 86 --Count; 87 } 88 89 // Ctrl flow can reach here if branch folding is run before IT block 90 // formation pass. 91 } 92 } 93 94 bool 95 Thumb2InstrInfo::isLegalToSplitMBBAt(MachineBasicBlock &MBB, 96 MachineBasicBlock::iterator MBBI) const { 97 while (MBBI->isDebugValue()) { 98 ++MBBI; 99 if (MBBI == MBB.end()) 100 return false; 101 } 102 103 unsigned PredReg = 0; 104 return llvm::getITInstrPredicate(MBBI, PredReg) == ARMCC::AL; 105 } 106 107 void Thumb2InstrInfo::copyPhysReg(MachineBasicBlock &MBB, 108 MachineBasicBlock::iterator I, DebugLoc DL, 109 unsigned DestReg, unsigned SrcReg, 110 bool KillSrc) const { 111 // Handle SPR, DPR, and QPR copies. 112 if (!ARM::GPRRegClass.contains(DestReg, SrcReg)) 113 return ARMBaseInstrInfo::copyPhysReg(MBB, I, DL, DestReg, SrcReg, KillSrc); 114 115 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg) 116 .addReg(SrcReg, getKillRegState(KillSrc))); 117 } 118 119 void Thumb2InstrInfo:: 120 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 121 unsigned SrcReg, bool isKill, int FI, 122 const TargetRegisterClass *RC, 123 const TargetRegisterInfo *TRI) const { 124 if (RC == ARM::GPRRegisterClass || RC == ARM::tGPRRegisterClass || 125 RC == ARM::tcGPRRegisterClass || RC == ARM::rGPRRegisterClass || 126 RC == ARM::GPRnopcRegisterClass) { 127 DebugLoc DL; 128 if (I != MBB.end()) DL = I->getDebugLoc(); 129 130 MachineFunction &MF = *MBB.getParent(); 131 MachineFrameInfo &MFI = *MF.getFrameInfo(); 132 MachineMemOperand *MMO = 133 MF.getMachineMemOperand( 134 MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)), 135 MachineMemOperand::MOStore, 136 MFI.getObjectSize(FI), 137 MFI.getObjectAlignment(FI)); 138 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::t2STRi12)) 139 .addReg(SrcReg, getKillRegState(isKill)) 140 .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 141 return; 142 } 143 144 ARMBaseInstrInfo::storeRegToStackSlot(MBB, I, SrcReg, isKill, FI, RC, TRI); 145 } 146 147 void Thumb2InstrInfo:: 148 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 149 unsigned DestReg, int FI, 150 const TargetRegisterClass *RC, 151 const TargetRegisterInfo *TRI) const { 152 if (RC == ARM::GPRRegisterClass || RC == ARM::tGPRRegisterClass || 153 RC == ARM::tcGPRRegisterClass || RC == ARM::rGPRRegisterClass || 154 RC == ARM::GPRnopcRegisterClass) { 155 DebugLoc DL; 156 if (I != MBB.end()) DL = I->getDebugLoc(); 157 158 MachineFunction &MF = *MBB.getParent(); 159 MachineFrameInfo &MFI = *MF.getFrameInfo(); 160 MachineMemOperand *MMO = 161 MF.getMachineMemOperand( 162 MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)), 163 MachineMemOperand::MOLoad, 164 MFI.getObjectSize(FI), 165 MFI.getObjectAlignment(FI)); 166 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::t2LDRi12), DestReg) 167 .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 168 return; 169 } 170 171 ARMBaseInstrInfo::loadRegFromStackSlot(MBB, I, DestReg, FI, RC, TRI); 172 } 173 174 void llvm::emitT2RegPlusImmediate(MachineBasicBlock &MBB, 175 MachineBasicBlock::iterator &MBBI, DebugLoc dl, 176 unsigned DestReg, unsigned BaseReg, int NumBytes, 177 ARMCC::CondCodes Pred, unsigned PredReg, 178 const ARMBaseInstrInfo &TII, unsigned MIFlags) { 179 bool isSub = NumBytes < 0; 180 if (isSub) NumBytes = -NumBytes; 181 182 // If profitable, use a movw or movt to materialize the offset. 183 // FIXME: Use the scavenger to grab a scratch register. 184 if (DestReg != ARM::SP && DestReg != BaseReg && 185 NumBytes >= 4096 && 186 ARM_AM::getT2SOImmVal(NumBytes) == -1) { 187 bool Fits = false; 188 if (NumBytes < 65536) { 189 // Use a movw to materialize the 16-bit constant. 190 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi16), DestReg) 191 .addImm(NumBytes) 192 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags); 193 Fits = true; 194 } else if ((NumBytes & 0xffff) == 0) { 195 // Use a movt to materialize the 32-bit constant. 196 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVTi16), DestReg) 197 .addReg(DestReg) 198 .addImm(NumBytes >> 16) 199 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags); 200 Fits = true; 201 } 202 203 if (Fits) { 204 if (isSub) { 205 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2SUBrr), DestReg) 206 .addReg(BaseReg, RegState::Kill) 207 .addReg(DestReg, RegState::Kill) 208 .addImm((unsigned)Pred).addReg(PredReg).addReg(0) 209 .setMIFlags(MIFlags); 210 } else { 211 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2ADDrr), DestReg) 212 .addReg(DestReg, RegState::Kill) 213 .addReg(BaseReg, RegState::Kill) 214 .addImm((unsigned)Pred).addReg(PredReg).addReg(0) 215 .setMIFlags(MIFlags); 216 } 217 return; 218 } 219 } 220 221 while (NumBytes) { 222 unsigned ThisVal = NumBytes; 223 unsigned Opc = 0; 224 if (DestReg == ARM::SP && BaseReg != ARM::SP) { 225 // mov sp, rn. Note t2MOVr cannot be used. 226 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),DestReg) 227 .addReg(BaseReg).setMIFlags(MIFlags)); 228 BaseReg = ARM::SP; 229 continue; 230 } 231 232 bool HasCCOut = true; 233 if (BaseReg == ARM::SP) { 234 // sub sp, sp, #imm7 235 if (DestReg == ARM::SP && (ThisVal < ((1 << 7)-1) * 4)) { 236 assert((ThisVal & 3) == 0 && "Stack update is not multiple of 4?"); 237 Opc = isSub ? ARM::tSUBspi : ARM::tADDspi; 238 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg) 239 .addReg(BaseReg).addImm(ThisVal/4).setMIFlags(MIFlags)); 240 NumBytes = 0; 241 continue; 242 } 243 244 // sub rd, sp, so_imm 245 Opc = isSub ? ARM::t2SUBri : ARM::t2ADDri; 246 if (ARM_AM::getT2SOImmVal(NumBytes) != -1) { 247 NumBytes = 0; 248 } else { 249 // FIXME: Move this to ARMAddressingModes.h? 250 unsigned RotAmt = CountLeadingZeros_32(ThisVal); 251 ThisVal = ThisVal & ARM_AM::rotr32(0xff000000U, RotAmt); 252 NumBytes &= ~ThisVal; 253 assert(ARM_AM::getT2SOImmVal(ThisVal) != -1 && 254 "Bit extraction didn't work?"); 255 } 256 } else { 257 assert(DestReg != ARM::SP && BaseReg != ARM::SP); 258 Opc = isSub ? ARM::t2SUBri : ARM::t2ADDri; 259 if (ARM_AM::getT2SOImmVal(NumBytes) != -1) { 260 NumBytes = 0; 261 } else if (ThisVal < 4096) { 262 Opc = isSub ? ARM::t2SUBri12 : ARM::t2ADDri12; 263 HasCCOut = false; 264 NumBytes = 0; 265 } else { 266 // FIXME: Move this to ARMAddressingModes.h? 267 unsigned RotAmt = CountLeadingZeros_32(ThisVal); 268 ThisVal = ThisVal & ARM_AM::rotr32(0xff000000U, RotAmt); 269 NumBytes &= ~ThisVal; 270 assert(ARM_AM::getT2SOImmVal(ThisVal) != -1 && 271 "Bit extraction didn't work?"); 272 } 273 } 274 275 // Build the new ADD / SUB. 276 MachineInstrBuilder MIB = 277 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg) 278 .addReg(BaseReg, RegState::Kill) 279 .addImm(ThisVal)).setMIFlags(MIFlags); 280 if (HasCCOut) 281 AddDefaultCC(MIB); 282 283 BaseReg = DestReg; 284 } 285 } 286 287 static unsigned 288 negativeOffsetOpcode(unsigned opcode) 289 { 290 switch (opcode) { 291 case ARM::t2LDRi12: return ARM::t2LDRi8; 292 case ARM::t2LDRHi12: return ARM::t2LDRHi8; 293 case ARM::t2LDRBi12: return ARM::t2LDRBi8; 294 case ARM::t2LDRSHi12: return ARM::t2LDRSHi8; 295 case ARM::t2LDRSBi12: return ARM::t2LDRSBi8; 296 case ARM::t2STRi12: return ARM::t2STRi8; 297 case ARM::t2STRBi12: return ARM::t2STRBi8; 298 case ARM::t2STRHi12: return ARM::t2STRHi8; 299 300 case ARM::t2LDRi8: 301 case ARM::t2LDRHi8: 302 case ARM::t2LDRBi8: 303 case ARM::t2LDRSHi8: 304 case ARM::t2LDRSBi8: 305 case ARM::t2STRi8: 306 case ARM::t2STRBi8: 307 case ARM::t2STRHi8: 308 return opcode; 309 310 default: 311 break; 312 } 313 314 return 0; 315 } 316 317 static unsigned 318 positiveOffsetOpcode(unsigned opcode) 319 { 320 switch (opcode) { 321 case ARM::t2LDRi8: return ARM::t2LDRi12; 322 case ARM::t2LDRHi8: return ARM::t2LDRHi12; 323 case ARM::t2LDRBi8: return ARM::t2LDRBi12; 324 case ARM::t2LDRSHi8: return ARM::t2LDRSHi12; 325 case ARM::t2LDRSBi8: return ARM::t2LDRSBi12; 326 case ARM::t2STRi8: return ARM::t2STRi12; 327 case ARM::t2STRBi8: return ARM::t2STRBi12; 328 case ARM::t2STRHi8: return ARM::t2STRHi12; 329 330 case ARM::t2LDRi12: 331 case ARM::t2LDRHi12: 332 case ARM::t2LDRBi12: 333 case ARM::t2LDRSHi12: 334 case ARM::t2LDRSBi12: 335 case ARM::t2STRi12: 336 case ARM::t2STRBi12: 337 case ARM::t2STRHi12: 338 return opcode; 339 340 default: 341 break; 342 } 343 344 return 0; 345 } 346 347 static unsigned 348 immediateOffsetOpcode(unsigned opcode) 349 { 350 switch (opcode) { 351 case ARM::t2LDRs: return ARM::t2LDRi12; 352 case ARM::t2LDRHs: return ARM::t2LDRHi12; 353 case ARM::t2LDRBs: return ARM::t2LDRBi12; 354 case ARM::t2LDRSHs: return ARM::t2LDRSHi12; 355 case ARM::t2LDRSBs: return ARM::t2LDRSBi12; 356 case ARM::t2STRs: return ARM::t2STRi12; 357 case ARM::t2STRBs: return ARM::t2STRBi12; 358 case ARM::t2STRHs: return ARM::t2STRHi12; 359 360 case ARM::t2LDRi12: 361 case ARM::t2LDRHi12: 362 case ARM::t2LDRBi12: 363 case ARM::t2LDRSHi12: 364 case ARM::t2LDRSBi12: 365 case ARM::t2STRi12: 366 case ARM::t2STRBi12: 367 case ARM::t2STRHi12: 368 case ARM::t2LDRi8: 369 case ARM::t2LDRHi8: 370 case ARM::t2LDRBi8: 371 case ARM::t2LDRSHi8: 372 case ARM::t2LDRSBi8: 373 case ARM::t2STRi8: 374 case ARM::t2STRBi8: 375 case ARM::t2STRHi8: 376 return opcode; 377 378 default: 379 break; 380 } 381 382 return 0; 383 } 384 385 bool llvm::rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx, 386 unsigned FrameReg, int &Offset, 387 const ARMBaseInstrInfo &TII) { 388 unsigned Opcode = MI.getOpcode(); 389 const MCInstrDesc &Desc = MI.getDesc(); 390 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); 391 bool isSub = false; 392 393 // Memory operands in inline assembly always use AddrModeT2_i12. 394 if (Opcode == ARM::INLINEASM) 395 AddrMode = ARMII::AddrModeT2_i12; // FIXME. mode for thumb2? 396 397 if (Opcode == ARM::t2ADDri || Opcode == ARM::t2ADDri12) { 398 Offset += MI.getOperand(FrameRegIdx+1).getImm(); 399 400 unsigned PredReg; 401 if (Offset == 0 && getInstrPredicate(&MI, PredReg) == ARMCC::AL) { 402 // Turn it into a move. 403 MI.setDesc(TII.get(ARM::tMOVr)); 404 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); 405 // Remove offset and remaining explicit predicate operands. 406 do MI.RemoveOperand(FrameRegIdx+1); 407 while (MI.getNumOperands() > FrameRegIdx+1); 408 MachineInstrBuilder MIB(&MI); 409 AddDefaultPred(MIB); 410 return true; 411 } 412 413 bool HasCCOut = Opcode != ARM::t2ADDri12; 414 415 if (Offset < 0) { 416 Offset = -Offset; 417 isSub = true; 418 MI.setDesc(TII.get(ARM::t2SUBri)); 419 } else { 420 MI.setDesc(TII.get(ARM::t2ADDri)); 421 } 422 423 // Common case: small offset, fits into instruction. 424 if (ARM_AM::getT2SOImmVal(Offset) != -1) { 425 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); 426 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset); 427 // Add cc_out operand if the original instruction did not have one. 428 if (!HasCCOut) 429 MI.addOperand(MachineOperand::CreateReg(0, false)); 430 Offset = 0; 431 return true; 432 } 433 // Another common case: imm12. 434 if (Offset < 4096 && 435 (!HasCCOut || MI.getOperand(MI.getNumOperands()-1).getReg() == 0)) { 436 unsigned NewOpc = isSub ? ARM::t2SUBri12 : ARM::t2ADDri12; 437 MI.setDesc(TII.get(NewOpc)); 438 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); 439 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset); 440 // Remove the cc_out operand. 441 if (HasCCOut) 442 MI.RemoveOperand(MI.getNumOperands()-1); 443 Offset = 0; 444 return true; 445 } 446 447 // Otherwise, extract 8 adjacent bits from the immediate into this 448 // t2ADDri/t2SUBri. 449 unsigned RotAmt = CountLeadingZeros_32(Offset); 450 unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xff000000U, RotAmt); 451 452 // We will handle these bits from offset, clear them. 453 Offset &= ~ThisImmVal; 454 455 assert(ARM_AM::getT2SOImmVal(ThisImmVal) != -1 && 456 "Bit extraction didn't work?"); 457 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal); 458 // Add cc_out operand if the original instruction did not have one. 459 if (!HasCCOut) 460 MI.addOperand(MachineOperand::CreateReg(0, false)); 461 462 } else { 463 464 // AddrMode4 and AddrMode6 cannot handle any offset. 465 if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6) 466 return false; 467 468 // AddrModeT2_so cannot handle any offset. If there is no offset 469 // register then we change to an immediate version. 470 unsigned NewOpc = Opcode; 471 if (AddrMode == ARMII::AddrModeT2_so) { 472 unsigned OffsetReg = MI.getOperand(FrameRegIdx+1).getReg(); 473 if (OffsetReg != 0) { 474 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); 475 return Offset == 0; 476 } 477 478 MI.RemoveOperand(FrameRegIdx+1); 479 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(0); 480 NewOpc = immediateOffsetOpcode(Opcode); 481 AddrMode = ARMII::AddrModeT2_i12; 482 } 483 484 unsigned NumBits = 0; 485 unsigned Scale = 1; 486 if (AddrMode == ARMII::AddrModeT2_i8 || AddrMode == ARMII::AddrModeT2_i12) { 487 // i8 supports only negative, and i12 supports only positive, so 488 // based on Offset sign convert Opcode to the appropriate 489 // instruction 490 Offset += MI.getOperand(FrameRegIdx+1).getImm(); 491 if (Offset < 0) { 492 NewOpc = negativeOffsetOpcode(Opcode); 493 NumBits = 8; 494 isSub = true; 495 Offset = -Offset; 496 } else { 497 NewOpc = positiveOffsetOpcode(Opcode); 498 NumBits = 12; 499 } 500 } else if (AddrMode == ARMII::AddrMode5) { 501 // VFP address mode. 502 const MachineOperand &OffOp = MI.getOperand(FrameRegIdx+1); 503 int InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm()); 504 if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub) 505 InstrOffs *= -1; 506 NumBits = 8; 507 Scale = 4; 508 Offset += InstrOffs * 4; 509 assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!"); 510 if (Offset < 0) { 511 Offset = -Offset; 512 isSub = true; 513 } 514 } else { 515 llvm_unreachable("Unsupported addressing mode!"); 516 } 517 518 if (NewOpc != Opcode) 519 MI.setDesc(TII.get(NewOpc)); 520 521 MachineOperand &ImmOp = MI.getOperand(FrameRegIdx+1); 522 523 // Attempt to fold address computation 524 // Common case: small offset, fits into instruction. 525 int ImmedOffset = Offset / Scale; 526 unsigned Mask = (1 << NumBits) - 1; 527 if ((unsigned)Offset <= Mask * Scale) { 528 // Replace the FrameIndex with fp/sp 529 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); 530 if (isSub) { 531 if (AddrMode == ARMII::AddrMode5) 532 // FIXME: Not consistent. 533 ImmedOffset |= 1 << NumBits; 534 else 535 ImmedOffset = -ImmedOffset; 536 } 537 ImmOp.ChangeToImmediate(ImmedOffset); 538 Offset = 0; 539 return true; 540 } 541 542 // Otherwise, offset doesn't fit. Pull in what we can to simplify 543 ImmedOffset = ImmedOffset & Mask; 544 if (isSub) { 545 if (AddrMode == ARMII::AddrMode5) 546 // FIXME: Not consistent. 547 ImmedOffset |= 1 << NumBits; 548 else { 549 ImmedOffset = -ImmedOffset; 550 if (ImmedOffset == 0) 551 // Change the opcode back if the encoded offset is zero. 552 MI.setDesc(TII.get(positiveOffsetOpcode(NewOpc))); 553 } 554 } 555 ImmOp.ChangeToImmediate(ImmedOffset); 556 Offset &= ~(Mask*Scale); 557 } 558 559 Offset = (isSub) ? -Offset : Offset; 560 return Offset == 0; 561 } 562 563 /// scheduleTwoAddrSource - Schedule the copy / re-mat of the source of the 564 /// two-addrss instruction inserted by two-address pass. 565 void 566 Thumb2InstrInfo::scheduleTwoAddrSource(MachineInstr *SrcMI, 567 MachineInstr *UseMI, 568 const TargetRegisterInfo &TRI) const { 569 if (SrcMI->getOpcode() != ARM::tMOVr || SrcMI->getOperand(1).isKill()) 570 return; 571 572 unsigned PredReg = 0; 573 ARMCC::CondCodes CC = llvm::getInstrPredicate(UseMI, PredReg); 574 if (CC == ARMCC::AL || PredReg != ARM::CPSR) 575 return; 576 577 // Schedule the copy so it doesn't come between previous instructions 578 // and UseMI which can form an IT block. 579 unsigned SrcReg = SrcMI->getOperand(1).getReg(); 580 ARMCC::CondCodes OCC = ARMCC::getOppositeCondition(CC); 581 MachineBasicBlock *MBB = UseMI->getParent(); 582 MachineBasicBlock::iterator MBBI = SrcMI; 583 unsigned NumInsts = 0; 584 while (--MBBI != MBB->begin()) { 585 if (MBBI->isDebugValue()) 586 continue; 587 588 MachineInstr *NMI = &*MBBI; 589 ARMCC::CondCodes NCC = llvm::getInstrPredicate(NMI, PredReg); 590 if (!(NCC == CC || NCC == OCC) || 591 NMI->modifiesRegister(SrcReg, &TRI) || 592 NMI->definesRegister(ARM::CPSR)) 593 break; 594 if (++NumInsts == 4) 595 // Too many in a row! 596 return; 597 } 598 599 if (NumInsts) { 600 MBB->remove(SrcMI); 601 MBB->insert(++MBBI, SrcMI); 602 } 603 } 604 605 ARMCC::CondCodes 606 llvm::getITInstrPredicate(const MachineInstr *MI, unsigned &PredReg) { 607 unsigned Opc = MI->getOpcode(); 608 if (Opc == ARM::tBcc || Opc == ARM::t2Bcc) 609 return ARMCC::AL; 610 return llvm::getInstrPredicate(MI, PredReg); 611 } 612
