| /external/llvm/lib/Target/ARM/ |
| ARMHazardRecognizer.cpp | 26 unsigned Opcode = MCID.getOpcode();
27 if (Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD)
85 unsigned Opcode = MI->getOpcode();
88 } else if (Opcode == ARM::t2IT) {
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| MLxExpansionPass.cpp | 144 unsigned Opcode = MCID.getOpcode();
145 if (Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD)
|
| /external/llvm/lib/Target/MBlaze/MCTargetDesc/ |
| MBlazeMCCodeEmitter.cpp | 182 unsigned Opcode = MI.getOpcode();
183 const MCInstrDesc &Desc = MCII.get(Opcode);
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCHazardRecognizers.cpp | 79 PPCHazardRecognizer970::GetInstrType(unsigned Opcode,
83 if ((int)Opcode >= 0) {
87 Opcode = ~Opcode;
89 const MCInstrDesc &MCID = TII.get(Opcode);
147 unsigned Opcode = Node->getMachineOpcode();
179 if (HasCTRSet && (Opcode == PPC::BCTRL_Darwin || Opcode == PPC::BCTRL_SVR4))
186 switch (Opcode) {
246 unsigned Opcode = Node->getMachineOpcode()
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelDAGToDAG.cpp | 165 unsigned Opcode = N->getOpcode() == ISD::SDIV ? SP::SDIVrr : SP::UDIVrr;
166 return CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS,
174 unsigned Opcode = N->getOpcode() == ISD::MULHU ? SP::UMULrr : SP::SMULrr;
175 SDNode *Mul = CurDAG->getMachineNode(Opcode, dl, MVT::i32, MVT::Glue,
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| SparcInstrInfo.cpp | 166 unsigned Opcode = I->getOpcode();
167 if (Opcode != SP::BCOND && Opcode != SP::FBCOND)
168 return true; //Unknown Opcode
194 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(Opcode))
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| /external/webkit/Source/JavaScriptCore/bytecode/ |
| Opcode.h | 196 macro(op_end, 2) // end must be the last opcode in the list
198 #define OPCODE_ID_ENUM(opcode, length) opcode,
208 #define OPCODE_LENGTH(opcode) opcode##_length
210 #define OPCODE_ID_LENGTH_MAP(opcode, length) length,
220 typedef void* Opcode;
222 typedef const void* Opcode;
225 typedef OpcodeID Opcode;
256 static void recordInstruction(int opcode);
[all...] |
| /external/llvm/lib/Target/MBlaze/ |
| MBlazeISelDAGToDAG.cpp | 190 unsigned Opcode = Node->getOpcode();
201 switch (Opcode) {
|
| /external/llvm/lib/Target/XCore/ |
| XCoreInstrInfo.cpp | 58 int Opcode = MI->getOpcode();
59 if (Opcode == XCore::LDWFI)
80 int Opcode = MI->getOpcode();
81 if (Opcode == XCore::STWFI)
129 /// the correspondent Branch instruction opcode.
142 /// opcode that matches the cc.
398 /// ReverseBranchCondition - Return the inverse opcode of the
|
| XCoreRegisterInfo.cpp | 147 int Opcode = isU6 ? XCore::EXTSP_u6 : XCore::EXTSP_lu6;
148 New=BuildMI(MF, Old->getDebugLoc(), TII.get(Opcode))
152 int Opcode = isU6 ? XCore::LDAWSP_ru6_RRegs : XCore::LDAWSP_lru6_RRegs;
153 New=BuildMI(MF, Old->getDebugLoc(), TII.get(Opcode), XCore::SP)
255 llvm_unreachable("Unexpected Opcode");
276 llvm_unreachable("Unexpected Opcode");
304 llvm_unreachable("Unexpected Opcode");
319 int Opcode = isImmU6(Value) ? XCore::LDC_ru6 : XCore::LDC_lru6;
320 BuildMI(MBB, I, dl, TII.get(Opcode), DstReg).addImm(Value);
|
| XCoreFrameLowering.cpp | 54 int Opcode = isU6 ? XCore::LDWSP_ru6 : XCore::LDWSP_lru6;
55 BuildMI(MBB, I, dl, TII.get(Opcode), DstReg)
69 int Opcode = isU6 ? XCore::STWSP_ru6 : XCore::STWSP_lru6;
70 BuildMI(MBB, I, dl, TII.get(Opcode))
127 int Opcode;
129 Opcode = (isU6) ? XCore::ENTSP_u6 : XCore::ENTSP_lu6;
134 Opcode = (isU6) ? XCore::EXTSP_u6 : XCore::EXTSP_lu6;
136 BuildMI(MBB, MBBI, dl, TII.get(Opcode)).addImm(FrameSize);
264 int Opcode = (isU6) ? XCore::RETSP_u6 : XCore::RETSP_lu6;
265 BuildMI(MBB, MBBI, dl, TII.get(Opcode)).addImm(FrameSize)
[all...] |
| /external/llvm/utils/TableGen/ |
| X86RecognizableInstr.h | 38 /// The opcode of the instruction, as used in an MCInst
44 /// The opcode field from the record; this is the opcode used in the Intel
46 uint8_t Opcode;
|
| /external/webkit/Source/WebCore/xml/ |
| XPathPredicate.h | 67 enum Opcode {
70 NumericOp(Opcode, Expression* lhs, Expression* rhs);
75 Opcode m_opcode;
80 enum Opcode { OP_EQ, OP_NE, OP_GT, OP_LT, OP_GE, OP_LE };
81 EqTestOp(Opcode, Expression* lhs, Expression* rhs);
87 Opcode m_opcode;
92 enum Opcode { OP_And, OP_Or };
93 LogicalOp(Opcode, Expression* lhs, Expression* rhs);
99 Opcode m_opcode;
|
| /external/llvm/include/llvm/MC/ |
| MCInst.h | 131 unsigned Opcode;
134 MCInst() : Opcode(0) {}
136 void setOpcode(unsigned Op) { Opcode = Op; }
138 unsigned getOpcode() const { return Opcode; }
|
| MCExpr.h | 230 enum Opcode {
238 Opcode Op;
241 MCUnaryExpr(Opcode _Op, const MCExpr *_Expr)
248 static const MCUnaryExpr *Create(Opcode Op, const MCExpr *Expr,
268 Opcode getOpcode() const { return Op; }
284 enum Opcode {
310 Opcode Op;
313 MCBinaryExpr(Opcode _Op, const MCExpr *_LHS, const MCExpr *_RHS)
320 static const MCBinaryExpr *Create(Opcode Op, const MCExpr *LHS,
400 Opcode getOpcode() const { return Op;
[all...] |
| MCInstrDesc.h | 135 unsigned short Opcode; // The opcode number
159 /// getOpcode - Return the opcode number for this descriptor.
161 return Opcode;
274 /// or zero if the encoding size cannot be known from the opcode.
|
| /external/llvm/lib/Target/Blackfin/ |
| BlackfinISelLowering.cpp | 130 const char *BlackfinTargetLowering::getTargetNodeName(unsigned Opcode) const {
131 switch (Opcode) {
429 unsigned Opcode = Op.getOpcode()==ISD::ADDE ? BF::ADD : BF::SUB;
438 SDNode *Sum = DAG.getMachineNode(Opcode, dl, MVT::i32, MVT::Glue,
446 Sum = DAG.getMachineNode(Opcode, dl, MVT::i32, MVT::Glue,
|
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelDAGToDAG.cpp | 336 unsigned Opcode = 0;
339 Opcode = MSP430::MOV8rm_POST;
342 Opcode = MSP430::MOV16rm_POST;
348 return CurDAG->getMachineNode(Opcode, N->getDebugLoc(),
|
| /external/llvm/lib/Target/Mips/ |
| MipsISelDAGToDAG.cpp | 190 unsigned Opcode = Node->getOpcode();
206 switch(Opcode) {
218 if (Opcode == ISD::ADDE) {
249 Op = (Opcode == ISD::UMUL_LOHI ? Mips::MULTu : Mips::MULT);
275 assert((Opcode == ISD::MUL || Node->getValueType(0) != MVT::i64) &&
281 unsigned MulOp = (Opcode == ISD::MULHU ?
289 if (Opcode == ISD::MUL) {
|
| /external/llvm/lib/Target/X86/Disassembler/ |
| X86Disassembler.cpp | 198 uint32_t Opcode = mcInst.getOpcode();
205 if (Opcode != X86::BLENDPSrri && Opcode != X86::BLENDPDrri &&
206 Opcode != X86::PBLENDWrri && Opcode != X86::MPSADBWrri &&
207 Opcode != X86::DPPSrri && Opcode != X86::DPPDrri &&
208 Opcode != X86::INSERTPSrr && Opcode != X86::VBLENDPSYrri &&
209 Opcode != X86::VBLENDPSYrmi && Opcode != X86::VBLENDPDYrri &
[all...] |
| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| X86MCCodeEmitter.cpp | 383 /// EmitVEXOpcodePrefix - AVX instructions are encoded using a opcode prefix
392 // VEX_R: opcode externsion equivalent to REX.R in
414 // VEX_W: opcode specific (use like REX.W, or used for
415 // opcode extension, or ignored, depending on the opcode byte)
421 // 0b00001: implied 0F leading opcode
422 // 0b00010: implied 0F 38 leading opcode bytes
423 // 0b00011: implied 0F 3A leading opcode bytes
439 // VEX_PP: opcode extension providing equivalent
449 // Encode the operand size opcode prefix as needed
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86MCInstLower.cpp | 231 static void SimplifyShortImmForm(MCInst &Inst, unsigned Opcode) {
246 Inst.setOpcode(Opcode);
252 unsigned Opcode) {
297 Inst.setOpcode(Opcode);
397 unsigned Opcode = OutMI.getOpcode();
400 OutMI.setOpcode(Opcode);
416 unsigned Opcode;
418 default: assert(0 && "Invalid opcode");
419 case X86::TAILJMPr: Opcode = X86::JMP32r; break;
421 case X86::TAILJMPd64: Opcode = X86::JMP_1; break
[all...] |
| X86RegisterInfo.cpp | 520 int Opcode = I->getOpcode();
521 bool isDestroy = Opcode == TII.getCallFrameDestroyOpcode();
542 if (Opcode == TII.getCallFrameSetupOpcode()) {
548 assert(Opcode == TII.getCallFrameDestroyOpcode());
571 if (Opcode == TII.getCallFrameDestroyOpcode() && CalleeAmt) {
|
| /external/llvm/lib/Transforms/Scalar/ |
| Reassociate.cpp | 202 /// opcode and if it only has one use.
203 static BinaryOperator *isReassociableOp(Value *V, unsigned Opcode) {
205 cast<Instruction>(V)->getOpcode() == Opcode)
275 unsigned Opcode = I->getOpcode();
278 BinaryOperator *LHSBO = isReassociableOp(LHS, Opcode);
279 BinaryOperator *RHSBO = isReassociableOp(RHS, Opcode);
286 LHSBO = isReassociableOp(LHS, Opcode);
290 RHSBO = isReassociableOp(RHS, Opcode);
325 assert(!isReassociableOp(RHS, Opcode) && "LinearizeExpr failed!");
662 static Value *OptimizeAndOrXor(unsigned Opcode,
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZISelDAGToDAG.cpp | 367 unsigned Opcode = Addr.getOpcode();
368 if (Opcode != ISD::Constant && Opcode != ISD::FrameIndex) {
416 unsigned Opcode = Addr.getOpcode();
417 if (Opcode != ISD::Constant && Opcode != ISD::FrameIndex) {
459 unsigned Opcode = Addr.getOpcode();
460 if (Opcode != ISD::Constant && Opcode != ISD::FrameIndex) {
508 unsigned Opcode = Addr.getOpcode()
[all...] |
