| /external/llvm/lib/Target/X86/ |
| X86FrameLowering.cpp | 103 unsigned Opc = MBBI->getOpcode();
104 switch (Opc) {
148 unsigned Opc = isSub ?
162 Opc = isSub
165 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opc))
175 BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
192 unsigned Opc = PI->getOpcode();
193 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
194 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &
[all...] |
| X86RegisterInfo.cpp | 554 unsigned Opc = getADDriOpcode(Is64Bit, Amount);
555 New = BuildMI(MF, DL, TII.get(Opc), StackPtr)
575 unsigned Opc = getSUBriOpcode(Is64Bit, CalleeAmt);
576 MachineInstr *New = BuildMI(MF, DL, TII.get(Opc), StackPtr)
610 unsigned Opc = MI.getOpcode();
611 bool AfterFPPop = Opc == X86::TAILJMPm64 || Opc == X86::TAILJMPm;
|
| /external/llvm/lib/Target/MBlaze/ |
| MBlazeInstrInfo.cpp | 196 unsigned Opc = MBlaze::BRID;
198 Opc = (unsigned)Cond[0].getImm();
202 BuildMI(&MBB, DL, get(Opc)).addMBB(TBB);
204 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg()).addMBB(TBB);
208 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg()).addMBB(TBB);
|
| MBlazeISelDAGToDAG.cpp | 101 unsigned Opc = N->getOpcode();
102 if (Opc != ISD::Constant)
213 unsigned Opc = MBlaze::ADDIK;
215 return CurDAG->SelectNodeTo(Node, Opc, VT, TFI, imm);
216 return CurDAG->getMachineNode(Opc, dl, VT, TFI, imm);
|
| MBlazeISelLowering.cpp | 369 unsigned Opc;
372 case MBlazeCC::EQ: Opc = MBlaze::BEQID; break;
373 case MBlazeCC::NE: Opc = MBlaze::BNEID; break;
374 case MBlazeCC::GT: Opc = MBlaze::BGTID; break;
375 case MBlazeCC::LT: Opc = MBlaze::BLTID; break;
376 case MBlazeCC::GE: Opc = MBlaze::BGEID; break;
377 case MBlazeCC::LE: Opc = MBlaze::BLEID; break;
393 BuildMI(MBB, dl, TII->get(Opc))
575 unsigned Opc;
579 Opc = MBlazeISD::Select_CC
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430FrameLowering.cpp | 142 unsigned Opc = PI->getOpcode();
143 if (Opc != MSP430::POP16r && !PI->getDesc().isTerminator())
|
| MSP430InstrInfo.cpp | 95 unsigned Opc;
97 Opc = MSP430::MOV16rr;
99 Opc = MSP430::MOV8rr;
103 BuildMI(MBB, I, DL, get(Opc), DestReg)
|
| MSP430ISelDAGToDAG.cpp | 364 unsigned Opc = (VT == MVT::i16 ? Opc16 : Opc8);
369 CurDAG->SelectNodeTo(Op, Opc,
|
| MSP430ISelLowering.cpp | 428 unsigned Opc = (CallConv == CallingConv::MSP430_INTR ?
432 return DAG.getNode(Opc, dl, MVT::Other, Chain, Flag);
435 return DAG.getNode(Opc, dl, MVT::Other, Chain);
594 unsigned Opc = Op.getOpcode();
601 switch (Opc) {
622 if (Opc == ISD::SRL && ShiftAmount) {
630 Victim = DAG.getNode((Opc == ISD::SHL ? MSP430ISD::RLA : MSP430ISD::RRA),
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZInstrInfo.cpp | 51 unsigned Opc = 0;
54 Opc = SystemZ::MOV32mr;
57 Opc = SystemZ::MOV64mr;
59 Opc = SystemZ::FMOV32mr;
61 Opc = SystemZ::FMOV64mr;
63 Opc = SystemZ::MOV64Pmr;
65 Opc = SystemZ::MOV128mr;
69 addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx)
81 unsigned Opc = 0;
84 Opc = SystemZ::MOV32rm
[all...] |
| SystemZFrameLowering.cpp | 69 unsigned Opc; uint64_t Chunk;
74 Opc = SystemZ::ADD64ri32;
77 Opc = SystemZ::ADD64ri16;
86 BuildMI(MBB, MBBI, DL, TII.get(Opc), SystemZ::R15D)
|
| SystemZISelDAGToDAG.cpp | 604 unsigned Opc, MOpc;
613 Opc = SystemZ::SDIVREM32r; MOpc = SystemZ::SDIVREM32m;
618 Opc = SystemZ::SDIVREM64r; MOpc = SystemZ::SDIVREM64m;
650 Result = CurDAG->getMachineNode(Opc, dl, ResVT, SDValue(Dividend, 0), N1);
684 unsigned Opc, MOpc, ClrOpc;
693 Opc = SystemZ::UDIVREM32r; MOpc = SystemZ::UDIVREM32m;
699 Opc = SystemZ::UDIVREM64r; MOpc = SystemZ::UDIVREM64m;
735 Result = CurDAG->getMachineNode(Opc, dl, ResVT, DivVal, N1);
|
| /external/llvm/lib/Target/ARM/ |
| Thumb1RegisterInfo.cpp | 128 int Opc = (isSub) ? ARM::tSUBrr : (isHigh ? ARM::tADDhirr : ARM::tADDrr);
130 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);
131 if (Opc != ARM::tADDhirr)
142 static unsigned calcNumMI(int Opc, int ExtraOpc, unsigned Bytes,
147 if (Opc == ARM::tADDrSPi) {
181 int Opc = 0;
189 Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
202 Opc = ARM::tADDrSPi;
211 Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
216 Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8
[all...] |
| ARMBaseRegisterInfo.cpp | 856 unsigned Opc = Old->getOpcode();
860 if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
867 assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
945 unsigned Opc = MI->getOpcode();
946 switch (Opc) {
[all...] |
| ARMExpandPseudoInsts.cpp | 64 unsigned Opc, bool IsExt, unsigned NumRegs);
608 unsigned Opc, bool IsExt, unsigned NumRegs) {
612 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc));
[all...] |
| Thumb2SizeReduction.cpp | 285 unsigned Opc = MI->getOpcode();
286 bool isPCOk = (Opc == ARM::t2LDMIA_RET || Opc == ARM::t2LDMIA ||
287 Opc == ARM::t2LDMDB || Opc == ARM::t2LDMIA_UPD ||
288 Opc == ARM::t2LDMDB_UPD);
289 bool isLROk = (Opc == ARM::t2STMIA_UPD || Opc == ARM::t2STMDB_UPD);
305 if (i == 1 && (Opc == ARM::t2LDRi12 || Opc == ARM::t2STRi12)
[all...] |
| /external/llvm/lib/Target/CellSPU/ |
| SPUInstrInfo.cpp | 33 unsigned opc = I->getOpcode(); local
35 return (opc == SPU::BR
36 || opc == SPU::BRA
37 || opc == SPU::BI);
42 unsigned opc = I->getOpcode(); local
44 return (opc == SPU::BRNZr32
45 || opc == SPU::BRNZv4i32
46 || opc == SPU::BRZr32
47 || opc == SPU::BRZv4i32
48 || opc == SPU::BRHNZr1
145 unsigned opc; local
180 unsigned opc; local
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsInstrInfo.cpp | 51 unsigned Opc = MI->getOpcode();
53 if ((Opc == Mips::LW) || (Opc == Mips::LW_P8) || (Opc == Mips::LD) ||
54 (Opc == Mips::LD_P8) || (Opc == Mips::LWC1) || (Opc == Mips::LWC1_P8) ||
55 (Opc == Mips::LDC1) || (Opc == Mips::LDC164) ||
56 (Opc == Mips::LDC164_P8))
[all...] |
| MipsAsmPrinter.cpp | 47 static bool isUnalignedLoadStore(unsigned Opc) {
48 return Opc == Mips::ULW || Opc == Mips::ULH || Opc == Mips::ULHu ||
49 Opc == Mips::USW || Opc == Mips::USH ||
50 Opc == Mips::ULW_P8 || Opc == Mips::ULH_P8 || Opc == Mips::ULHu_P8 ||
51 Opc == Mips::USW_P8 || Opc == Mips::USH_P8
[all...] |
| MipsISelDAGToDAG.cpp | 212 unsigned Opc = InFlag.getOpcode(); (void)Opc;
213 assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) ||
214 (Opc == ISD::SUBC || Opc == ISD::SUBE)) &&
290 unsigned Opc = (Ty == MVT::i32 ? Mips::MFLO : Mips::MFLO64);
291 return CurDAG->getMachineNode(Opc, dl, Ty, InFlag);
|
| /external/llvm/lib/Target/XCore/ |
| XCoreInstrInfo.cpp | 290 unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm());
291 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg())
299 unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm());
300 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg())
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCInstrInfo.cpp | 314 unsigned Opc;
316 Opc = PPC::OR;
318 Opc = PPC::OR8;
320 Opc = PPC::FMR;
322 Opc = PPC::MCRF;
324 Opc = PPC::VOR;
326 Opc = PPC::CROR;
330 const MCInstrDesc &MCID = get(Opc);
|
| PPCISelDAGToDAG.cpp | 305 static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) {
306 return N->getOpcode() == Opc
449 unsigned Opc;
478 Opc = PPC::CMPLW;
483 Opc = PPC::CMPLW;
490 Opc = PPC::CMPW;
521 Opc = PPC::CMPLD;
526 Opc = PPC::CMPLD;
533 Opc = PPC::CMPD;
536 Opc = PPC::FCMPUS
[all...] |
| /external/llvm/lib/Target/Alpha/ |
| AlphaISelDAGToDAG.cpp | 306 unsigned Opc = Alpha::WTF;
312 Opc = Alpha::CMPTEQ; break;
314 Opc = Alpha::CMPTLT; break;
316 Opc = Alpha::CMPTLE; break;
318 Opc = Alpha::CMPTLT; rev = true; break;
320 Opc = Alpha::CMPTLE; rev = true; break;
322 Opc = Alpha::CMPTEQ; inv = true; break;
324 Opc = Alpha::CMPTUN; inv = true; break;
326 Opc = Alpha::CMPTUN; break;
330 SDNode *cmp = CurDAG->getMachineNode(Opc, dl, MVT::f64, tmp1, tmp2)
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| ScheduleDAGSDNodes.cpp | 258 unsigned Opc = Node->getMachineOpcode();
259 const MCInstrDesc &MCID = TII->get(Opc);
393 unsigned Opc = MainNode->getMachineOpcode();
394 const MCInstrDesc &MCID = TII->get(Opc);
|
