| /external/llvm/lib/CodeGen/ |
| CallingConvLower.cpp | 122 unsigned NumOps = Outs.size();
123 for (unsigned i = 0; i != NumOps; ++i) {
141 unsigned NumOps = ArgVTs.size();
142 for (unsigned i = 0; i != NumOps; ++i) {
|
| TwoAddressInstructionPass.cpp | 455 unsigned NumOps = MI.isInlineAsm()
457 for (unsigned i = 0; i != NumOps; ++i) {
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86CodeEmitter.cpp | 159 unsigned NumOps = Desc.getNumOperands();
160 if (NumOps) {
161 bool isTwoAddr = NumOps > 1 &&
166 for (unsigned e = NumOps; i != e; ++i) {
184 for (unsigned e = NumOps; i != e; ++i) {
196 for (; i != NumOps; ++i) {
213 if (NumOps > e && X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(e)))
230 for (unsigned e = NumOps; i != e; ++i) {
701 unsigned NumOps = Desc->getNumOperands();
703 if (NumOps > 1 && Desc->getOperandConstraint(1, MCOI::TIED_TO) != -1
[all...] |
| X86InstrInfo.cpp | [all...] |
| X86ISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| X86MCCodeEmitter.cpp | 642 unsigned NumOps = MI.getNumOperands();
644 bool isTwoAddr = NumOps > 1 &&
649 for (; i != NumOps; ++i) {
667 for (; i != NumOps; ++i) {
679 for (; i != NumOps; ++i) {
696 if (NumOps > e && MI.getOperand(e).isReg() &&
715 for (unsigned e = NumOps; i != e; ++i) {
866 unsigned NumOps = Desc.getNumOperands();
868 if (NumOps > 1 && Desc.getOperandConstraint(1, MCOI::TIED_TO) != -1)
870 else if (NumOps > 2 && Desc.getOperandConstraint(NumOps-1, MCOI::TIED_TO)== 0
[all...] |
| /external/llvm/utils/TableGen/ |
| CodeGenInstruction.cpp | 71 unsigned NumOps = 1;
92 NumOps = NumArgs;
117 OperandType, MIOperandNo, NumOps,
119 MIOperandNo += NumOps;
|
| DAGISelMatcherEmitter.cpp | 647 unsigned NumOps = P.getNumOperands();
650 ++NumOps; // Get the chained node too.
653 OS << " Result.resize(NextRes+" << NumOps << ");\n";
668 for (unsigned i = 0; i != NumOps; ++i)
|
| AsmWriterEmitter.cpp | 352 unsigned NumOps = NumInstOpsHandled[InstIdxs[i]];
353 assert(NumOps <= Inst->Operands.size() &&
356 Inst->Operands.begin()+NumOps);
765 unsigned NumOps = 0;
769 ++NumOps;
773 return NumOps;
777 unsigned NumOps = 0;
789 ++NumOps;
794 return NumOps;
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| ScheduleDAGFast.cpp | 482 unsigned NumOps = Node->getNumOperands();
483 if (Node->getOperand(NumOps-1).getValueType() == MVT::Glue)
484 --NumOps; // Ignore the glue operand.
486 for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) {
|
| LegalizeTypes.cpp | 419 for (unsigned i = 0, NumOps = I->getNumOperands(); i < NumOps; ++i)
[all...] |
| ScheduleDAGSDNodes.cpp | 173 unsigned NumOps = Node->getNumOperands();
174 if (Node->getOperand(NumOps-1).getValueType() == MVT::Other)
175 Chain = Node->getOperand(NumOps-1).getNode();
|
| LegalizeVectorTypes.cpp | [all...] |
| ScheduleDAGRRList.cpp | [all...] |
| /external/llvm/lib/Target/ARM/ |
| Thumb2SizeReduction.cpp | 629 unsigned NumOps = MCID.getNumOperands();
630 HasCC = (MI->getOperand(NumOps-1).getReg() == ARM::CPSR);
631 if (HasCC && MI->getOperand(NumOps-1).isDead())
655 unsigned NumOps = MCID.getNumOperands();
657 if (i < NumOps && MCID.OpInfo[i].isOptionalDef())
719 unsigned NumOps = MCID.getNumOperands();
720 HasCC = (MI->getOperand(NumOps-1).getReg() == ARM::CPSR);
721 if (HasCC && MI->getOperand(NumOps-1).isDead())
745 unsigned NumOps = MCID.getNumOperands();
747 if (i < NumOps && MCID.OpInfo[i].isOptionalDef()
[all...] |
| ARMBaseInstrInfo.cpp | 149 unsigned NumOps = MCID.getNumOperands();
153 const MachineOperand &Offset = MI->getOperand(NumOps-3);
157 unsigned OffImm = MI->getOperand(NumOps-2).getImm();
158 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm();
595 unsigned NumOps = MCID.getNumOperands();
597 MI->getOperand(NumOps - (MCID.isPredicable() ? 3 : 2));
[all...] |
| ARMConstantIslandPass.cpp | [all...] |
| /external/llvm/lib/Bitcode/Writer/ |
| BitcodeWriter.cpp | 842 unsigned NumOps = CA->getNumOperands();
844 if (CA->getOperand(NumOps-1)->isNullValue()) {
846 --NumOps; // Don't encode the null, which isn't allowed by char6.
[all...] |
| /frameworks/compile/slang/BitWriter_2_9/ |
| BitcodeWriter.cpp | [all...] |
| /external/llvm/lib/Target/ARM/Disassembler/ |
| ARMDisassembler.cpp | 567 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
569 for (unsigned i = 0; i < NumOps; ++i, ++I) {
634 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
636 for (unsigned i = 0; i < NumOps; ++i, ++I) {
674 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
675 for (unsigned i = 0; i < NumOps; ++i, ++I) {
[all...] |
| /external/llvm/lib/VMCore/ |
| Instructions.cpp | 143 unsigned NumOps = e + e / 2;
144 if (NumOps < 2) NumOps = 2; // 2 op PHI nodes are VERY common.
149 ReservedSpace = NumOps;
[all...] |
| /external/llvm/lib/Target/CellSPU/ |
| SPUISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | [all...] |
