| /external/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 201 // like ADDC/SUBC, which indicate the carry result is always false.
208 ADDC, SUBC,
[all...] |
| SelectionDAG.h | [all...] |
| /external/llvm/lib/Target/MBlaze/ |
| MBlazeDelaySlotFiller.cpp | 196 op == MBlaze::ADDC || op == MBlaze::ADDIC ||
|
| /external/llvm/lib/Target/Mips/ |
| MipsISelDAGToDAG.cpp | 213 assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) ||
|
| MipsISelLowering.cpp | 245 // (addc multLo, Lo0), (adde multHi, Hi0),
252 // ADDENode's second operand must be a flag output of an ADDC node in order
256 if (ADDCNode->getOpcode() != ISD::ADDC)
307 // replace uses of adde and addc here
319 // (addc Lo0, multLo), (sube Hi0, multHi),
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.h | 74 ADDC, // Add with carry
|
| ARMISelLowering.cpp | 568 setOperationAction(ISD::ADDC, MVT::i32, Custom);
[all...] |
| /external/qemu/tcg/ppc/ |
| tcg-target.c | 347 #define ADDC XO31( 10)
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeIntegerTypes.cpp | [all...] |
| DAGCombiner.cpp | [all...] |
| SelectionDAG.cpp | [all...] |
| /external/llvm/lib/Target/MBlaze/Disassembler/ |
| MBlazeDisassembler.cpp | 41 MBlaze::ADD, MBlaze::RSUB, MBlaze::ADDC, MBlaze::RSUBC, //00,01,02,03
|
| /external/llvm/lib/Target/Alpha/ |
| AlphaISelLowering.cpp | 102 setOperationAction(ISD::ADDC , MVT::i64, Expand);
[all...] |
| /external/qemu/tcg/ppc64/ |
| tcg-target.c | 337 #define ADDC XO31( 10)
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelDAGToDAG.cpp | 316 case ISD::ADDC:
[all...] |
| X86ISelLowering.cpp | 361 setOperationAction(ISD::ADDC, VT, Custom);
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreISelLowering.cpp | 89 setOperationAction(ISD::ADDC, MVT::i32, Expand);
[all...] |
