| /external/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 235 FADD, FSUB, FMUL, FMA, FDIV, FREM,
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZISelLowering.cpp | 146 setOperationAction(ISD::FMA, MVT::f32, Expand);
147 setOperationAction(ISD::FMA, MVT::f64, Expand);
[all...] |
| /external/llvm/lib/Target/Alpha/ |
| AlphaISelLowering.cpp | 126 setOperationAction(ISD::FMA, MVT::f64, Expand);
127 setOperationAction(ISD::FMA, MVT::f32, Expand);
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | 759 setOperationAction(ISD::FMA , MVT::f64, Expand);
763 setOperationAction(ISD::FMA , MVT::f32, Expand);
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeFloatTypes.cpp | 78 case ISD::FMA: R = SoftenFloatRes_FMA(N); break;
[all...] |
| LegalizeDAG.cpp | [all...] |
| SelectionDAG.cpp | [all...] |
| SelectionDAGBuilder.cpp | [all...] |
| /external/llvm/lib/Target/MBlaze/ |
| MBlazeISelLowering.cpp | 73 setOperationAction(ISD::FMA, MVT::f32, Expand);
[all...] |
| /external/llvm/lib/Target/CellSPU/ |
| SPUISelLowering.cpp | 224 setOperationAction(ISD::FMA, MVT::f64, Expand);
225 setOperationAction(ISD::FMA, MVT::f32, Expand);
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | 181 setOperationAction(ISD::FMA, MVT::f32, Expand);
182 setOperationAction(ISD::FMA, MVT::f64, Expand);
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 128 setOperationAction(ISD::FMA , MVT::f64, Expand);
133 setOperationAction(ISD::FMA , MVT::f32, Expand);
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | 638 // We don't support FMA.
639 setOperationAction(ISD::FMA, MVT::f64, Expand);
640 setOperationAction(ISD::FMA, MVT::f32, Expand);
667 setOperationAction(ISD::FMA, MVT::f80, Expand);
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | [all...] |
