/external/llvm/lib/CodeGen/ |
RegisterClassInfo.h | 30 unsigned NumRegs; 34 RCInfo() : Tag(0), NumRegs(0), ProperSubClass(false) {} 36 return makeArrayRef(Order.get(), NumRegs); 81 return get(RC).NumRegs;
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RegisterClassInfo.cpp | 74 unsigned NumRegs = RC->getNumRegs(); 77 RCI.Order.reset(new unsigned[NumRegs]); 96 RCI.NumRegs = N + CSRAlias.size(); 97 assert (RCI.NumRegs <= NumRegs && "Allocation order larger than regclass"); 104 if (Super != RC && getNumAllocatableRegs(Super) > RCI.NumRegs) 109 for (unsigned I = 0; I != RCI.NumRegs; ++I)
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RegAllocBase.h | 73 unsigned NumRegs; 76 LiveUnionArray(): NumRegs(0), Array(0) {} 79 unsigned numRegs() const { return NumRegs; } 86 assert(PhysReg < NumRegs && "physReg out of bounds");
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VirtRegMap.cpp | 93 unsigned NumRegs = MF->getRegInfo().getNumVirtRegs(); 94 Virt2PhysMap.resize(NumRegs); 95 Virt2StackSlotMap.resize(NumRegs); 96 Virt2ReMatIdMap.resize(NumRegs); 97 Virt2SplitMap.resize(NumRegs); 98 Virt2SplitKillMap.resize(NumRegs); 99 ReMatMap.resize(NumRegs); 100 ImplicitDefed.resize(NumRegs); 227 unsigned NumRegs = TRI->getNumRegs(); 229 UnusedRegs.resize(NumRegs); [all...] |
ExecutionDepsFix.cpp | 116 const unsigned NumRegs; 124 : MachineFunctionPass(ID), RC(rc), NumRegs(RC->getNumRegs()) {} 186 assert(unsigned(rx) < NumRegs && "Invalid index"); 188 LiveRegs = new DomainValue*[NumRegs]; 189 std::fill(LiveRegs, LiveRegs+NumRegs, (DomainValue*)0); 204 assert(unsigned(rx) < NumRegs && "Invalid index"); 217 assert(unsigned(rx) < NumRegs && "Invalid index"); 249 for (unsigned rx = 0; rx != NumRegs; ++rx) 268 for (unsigned rx = 0; rx != NumRegs; ++rx) 457 assert(NumRegs == RC->getNumRegs() && "Bad regclass") [all...] |
RegAllocBasic.cpp | 186 unionVRegs(new LiveVirtRegBitSet[PhysReg2LiveUnion.numRegs()]); 189 for (unsigned PhysReg = 0; PhysReg < PhysReg2LiveUnion.numRegs(); ++PhysReg) { 223 NumRegs = NRegs; 238 const unsigned NumRegs = TRI->getNumRegs(); 239 if (NumRegs != PhysReg2LiveUnion.numRegs()) { 240 PhysReg2LiveUnion.init(UnionAllocator, NumRegs); 242 Queries.reset(new LiveIntervalUnion::Query[PhysReg2LiveUnion.numRegs()]); 249 for (unsigned r = 0; r != NumRegs; ++r) 252 NumRegs = 0 [all...] |
LiveVariables.cpp | 487 unsigned NumRegs = TRI->getNumRegs(); 488 PhysRegDef = new MachineInstr*[NumRegs]; 489 PhysRegUse = new MachineInstr*[NumRegs]; 491 std::fill(PhysRegDef, PhysRegDef + NumRegs, (MachineInstr*)0); 492 std::fill(PhysRegUse, PhysRegUse + NumRegs, (MachineInstr*)0); 612 for (unsigned i = 0; i != NumRegs; ++i) 616 std::fill(PhysRegDef, PhysRegDef + NumRegs, (MachineInstr*)0); 617 std::fill(PhysRegUse, PhysRegUse + NumRegs, (MachineInstr*)0);
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MachineLICM.cpp | 464 unsigned NumRegs = TRI->getNumRegs(); 465 unsigned *PhysRegDefs = new unsigned[NumRegs]; 466 std::fill(PhysRegDefs, PhysRegDefs + NumRegs, 0); [all...] |
/external/llvm/include/llvm/CodeGen/ |
CallingConvLower.h | 231 /// NumRegs if they are all allocated. 232 unsigned getFirstUnallocated(const unsigned *Regs, unsigned NumRegs) const { 233 for (unsigned i = 0; i != NumRegs; ++i) 236 return NumRegs; 259 unsigned AllocateReg(const unsigned *Regs, unsigned NumRegs) { 260 unsigned FirstUnalloc = getFirstUnallocated(Regs, NumRegs); 261 if (FirstUnalloc == NumRegs) 272 unsigned NumRegs) { 273 unsigned FirstUnalloc = getFirstUnallocated(Regs, NumRegs); 274 if (FirstUnalloc == NumRegs) [all...] |
FastISel.h | 326 void UpdateValueMap(const Value* I, unsigned Reg, unsigned NumRegs = 1);
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/external/llvm/include/llvm/MC/ |
MCRegisterInfo.h | 141 unsigned NumRegs; // Number of entries in the array 157 NumRegs = NR; 199 assert(RegNo < NumRegs && 256 return NumRegs;
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/external/llvm/lib/Target/ARM/ |
ARMExpandPseudoInsts.cpp | 64 unsigned Opc, bool IsExt, unsigned NumRegs); 107 unsigned char NumRegs; // D registers loaded or stored 415 unsigned NumRegs = TableEntry->NumRegs; 427 if (NumRegs > 2) 429 if (NumRegs > 3) 479 unsigned NumRegs = TableEntry->NumRegs; 499 if (NumRegs > 2) 501 if (NumRegs > 3 [all...] |
Thumb1FrameLowering.cpp | 366 bool NumRegs = false; 378 NumRegs = true; 382 if (NumRegs)
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ARMBaseRegisterInfo.cpp | 246 unsigned NumRegs = SubIndices.size(); 247 if (NumRegs == 8) { 258 } else if (NumRegs == 4) { 295 } else if (NumRegs == 2) { [all...] |
ARMLoadStoreOptimizer.cpp | 296 unsigned NumRegs = Regs.size(); 297 if (NumRegs <= 1) 306 else if (Offset == -4 * (int)NumRegs + 4 && haveIBAndDA) 308 else if (Offset == -4 * (int)NumRegs && isNotVFP) 319 if (NumRegs <= 2) 326 NewBase = Regs[NumRegs-1].first; 358 for (unsigned i = 0; i != NumRegs; ++i) [all...] |
ARMBaseInstrInfo.cpp | [all...] |
ARMCodeEmitter.cpp | [all...] |
ARMISelDAGToDAG.cpp | [all...] |
/external/llvm/lib/CodeGen/SelectionDAG/ |
SelectionDAGBuilder.cpp | 229 unsigned NumRegs = 232 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); 233 NumParts = NumRegs; // Silence a compiler warning. 500 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, 505 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); 506 NumParts = NumRegs; // Silence a compiler warning. 586 unsigned NumRegs = tli.getNumRegisters(Context, ValueVT); 588 for (unsigned i = 0; i != NumRegs; ++i) 591 Reg += NumRegs; 657 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT) [all...] |
FunctionLoweringInfo.cpp | 228 unsigned NumRegs = TLI.getNumRegisters(Ty->getContext(), ValueVT); 229 for (unsigned i = 0; i != NumRegs; ++i) {
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FastISel.cpp | 243 void FastISel::UpdateValueMap(const Value *I, unsigned Reg, unsigned NumRegs) { 255 for (unsigned i = 0; i < NumRegs; i++) [all...] |
/external/llvm/lib/Transforms/Scalar/ |
LoopStrengthReduce.cpp | 672 unsigned NumRegs; 681 : NumRegs(0), AddRecCost(0), NumIVMuls(0), NumBaseAdds(0), ImmCost(0), 691 return ((NumRegs | AddRecCost | NumIVMuls | NumBaseAdds 693 || ((NumRegs & AddRecCost & NumIVMuls & NumBaseAdds 700 return NumRegs == ~0u; 778 ++NumRegs; 851 NumRegs = ~0u; 861 if (NumRegs != Other.NumRegs) 862 return NumRegs < Other.NumRegs [all...] |
/external/llvm/lib/Target/ARM/MCTargetDesc/ |
ARMMCCodeEmitter.cpp | [all...] |
/external/v8/src/ |
frames.h | 40 int NumRegs(RegList list);
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/external/llvm/lib/Target/X86/ |
X86FastISel.cpp | [all...] |