| /external/valgrind/main/memcheck/tests/amd64-linux/ |
| int3-amd64.stdout.exp | 2 in int_handler, RIP is ...
|
| /prebuilt/linux-x86/toolchain/i686-linux-glibc2.7-4.4.3/sysroot/usr/include/sys/ |
| reg.h | 44 # define RIP 16
|
| /bionic/libc/kernel/arch-x86/asm/ |
| ptrace-abi.h | 57 #define RIP 128
|
| /development/ndk/platforms/android-9/arch-x86/include/asm/ |
| ptrace-abi.h | 57 #define RIP 128
|
| /external/kernel-headers/original/asm-x86/ |
| ptrace-abi.h | 47 #define RIP 128
|
| /prebuilt/linux-x86/toolchain/i686-linux-glibc2.7-4.4.3/sysroot/usr/include/asm/ |
| ptrace-abi.h | 47 #define RIP 128
|
| /prebuilt/ndk/android-ndk-r4/platforms/android-5/arch-x86/usr/include/asm/ |
| ptrace-abi.h | 57 #define RIP 128
|
| /prebuilt/ndk/android-ndk-r4/platforms/android-8/arch-x86/usr/include/asm/ |
| ptrace-abi.h | 57 #define RIP 128
|
| /prebuilt/ndk/android-ndk-r6/platforms/android-9/arch-x86/usr/include/asm/ |
| ptrace-abi.h | 57 #define RIP 128
|
| /external/netcat/data/ |
| rip.d | 5 # struct rip {
22 ### RIP packet redux
|
| /external/valgrind/main/VEX/auxprogs/ |
| genoffsets.c | 115 GENOFFSET(AMD64,amd64,RIP);
|
| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| X86MCTargetDesc.cpp | 343 ? X86::RIP // Should have dwarf #16.
381 MachineLocation CSSrc(is64Bit ? X86::RIP : X86::EIP);
396 // Win64 requires rip-rel addressing, thus we force it to PIC. Otherwise we
|
| X86AsmBackend.cpp | 230 // Check if it has an expression and is not RIP relative.
238 if (Op.isReg() && Op.getReg() == X86::RIP)
|
| X86MCCodeEmitter.cpp | 251 // Handle %rip relative addressing.
252 if (BaseReg == X86::RIP) { // [disp32+RIP] in X86-64 mode
253 assert(is64BitMode() && "Rip-relative addressing requires 64-bit mode");
254 assert(IndexReg.getReg() == 0 && "Invalid rip-relative address");
265 // rip-relative addressing is actually relative to the *next* instruction.
280 // If no BaseReg, issue a RIP relative instruction only if the MCE can
291 // byte to emit an addr that is just 'disp32' (the non-RIP relative form).
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86CodeEmitter.cpp | 419 // But it's probably not beneficial. If the MCE supports using RIP directly
421 // 89 05 00 00 00 00 mov %eax,0(%rip) # PC-relative
473 // Handle %rip relative addressing.
474 if (BaseReg == X86::RIP ||
475 (Is64BitMode && DispForReloc)) { // [disp32+RIP] in X86-64 mode
477 "Invalid rip-relative address");
485 // while others, unless explicit asked to use RIP, use absolute references.
489 // If no BaseReg, issue a RIP relative instruction only if the MCE can
493 if (BaseReg != 0 && BaseReg != X86::RIP)
503 // byte to emit an addr that is just 'disp32' (the non-RIP relative form)
[all...] |
| X86AsmPrinter.cpp | 286 // If we really don't want to print out (rip), don't.
288 if (HasBaseReg && Modifier && !strcmp(Modifier, "no-rip") &&
289 BaseReg.getReg() == X86::RIP)
391 O << "(%rip)";
468 printMemReference(MI, OpNo, O, "no-rip");
|
| X86FastISel.cpp | 500 // RIP-relative addresses can't have additional register operands, so if
521 // Use rip-relative addressing if we can. Above we verified that the
524 AM.Base.Reg = X86::RIP;
553 StubAM.Base.Reg = X86::RIP;
633 // RIP-relative addresses can't have additional register operands.
653 // Use rip-relative addressing if we can. Above we verified that the
656 AM.Base.Reg = X86::RIP;
[all...] |
| X86RegisterInfo.cpp | 56 ? X86::RIP : X86::EIP,
400 Reserved.set(X86::RIP);
|
| X86ISelDAGToDAG.cpp | 89 /// isRIPRelative - Return true if this addressing mode is already RIP
95 return RegNode->getReg() == X86::RIP;
238 // These are 32-bit even in 64-bit mode since RIP relative offset
622 // Handle X86-64 rip-relative addresses. We check this before checking direct
623 // folding because RIP is preferable to non-RIP accesses.
629 // Base and index reg must be 0 in order to use %rip as base and lowering
630 // must allow RIP.
661 AM.setBaseReg(CurDAG->getRegister(X86::RIP, MVT::i64));
667 // mode, this results in a non-RIP-relative computation
[all...] |
| X86MCInstLower.cpp | 552 LEA.addOperand(MCOperand::CreateReg(X86::RIP)); // base
|
| /external/llvm/lib/Target/X86/Disassembler/ |
| X86Disassembler.cpp | 363 baseReg = MCOperand::CreateReg(X86::RIP); // Section 2.2.1.6
|
| X86DisassemblerDecoder.h | 291 ENTRY(RIP)
|
| /external/valgrind/main/coregrind/m_sigframe/ |
| sigframe-amd64-linux.c | 361 SC2(rip,RIP);
528 "next %%RIP = %#llx, status=%d\n",
586 tst->arch.vex.guest_RIP = sc->rip;
629 "VG_(signal_return) (thread %d): isRT=%d valid magic; RIP=%#llx\n",
|
| /external/llvm/lib/Transforms/Scalar/ |
| ObjCARC.cpp | [all...] |
| /external/iproute2/doc/ |
| ip-tunnels.tex | 92 with ttl 1 will reach peering host (f.e.\ RIP, OSPF or EBGP)
|
