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Searched
refs:Registers
(Results
1 - 17
of
17
) sorted by null
/external/v8/src/arm/
constants-arm.cc
61
const char*
Registers
::names_[kNumRegisters] = {
67
// List of alias names which can be used when referring to ARM
registers
.
68
const
Registers
::RegisterAlias
Registers
::aliases_[] = {
79
const char*
Registers
::Name(int reg) {
90
// Support for VFP
registers
s0 to s31 (d0 to d15).
128
int
Registers
::Number(const char* name) {
constants-arm.h
94
// Number of
registers
in normal ARM mode.
442
// These constants are declared in assembler-arm.cc, as they use named
registers
739
class
Registers
{
simulator-arm.cc
183
int regnum =
Registers
::Number(desc);
321
PrintF("%3s: 0x%08x %10d",
Registers
::Name(i), value, value);
438
int regnum =
Registers
::Number(arg1);
566
PrintF(" use register name 'all' to print all
registers
\n");
746
// All
registers
are initialized to zero to start with.
755
// Initializing VFP
registers
.
756
// All
registers
are initialized to zero to start with
758
// physical
registers
in the target.
869
// Simulator internal state for special
registers
such as PC.
929
// Getting from and setting into VFP
registers
[
all
...]
/external/v8/src/mips/
constants-mips.cc
39
//
Registers
44
const char*
Registers
::names_[kNumSimuRegisters] = {
61
// List of alias names which can be used when referring to MIPS
registers
.
62
const
Registers
::RegisterAlias
Registers
::aliases_[] = {
70
const char*
Registers
::Name(int reg) {
81
int
Registers
::Number(const char* name) {
109
// List of alias names which can be used when referring to MIPS
registers
.
simulator-mips.cc
79
// Print all
registers
with a nice formatting.
204
int regnum =
Registers
::Number(desc);
263
#define REG_INFO(n)
Registers
::Name(n), GetRegisterValue(n), GetRegisterValue(n)
404
int regnum =
Registers
::Number(arg1);
564
// Print
registers
and disassemble
608
PrintF(" use register name 'all' to print all
registers
\n");
766
// All
registers
are initialized to zero to start with.
873
// Simulator internal state for special
registers
such as PC.
[
all
...]
constants-mips.h
61
//
Registers
and FPURegister.
63
// Number of general purpose
registers
.
67
// Number of
registers
with HI, LO, and pc.
73
// Number coprocessor
registers
.
77
// FPU (coprocessor 1) control
registers
. Currently only FCSR is implemented.
87
class
Registers
{
488
//
registers
and other constants.
/external/llvm/utils/TableGen/
CodeGenRegisters.cpp
78
// Add this as a super-register of SR now all sub-
registers
are in the list.
80
// order getSubRegs is called on all
registers
.
146
assert(SubRegsComplete && "Must precompute sub-
registers
");
159
// A RegisterTuples def is used to generate pseudo-
registers
from lists of
160
// sub-
registers
. We provide a SetTheory expander class that returns the new
161
//
registers
.
171
throw TGError(Def->getLoc(), "Tuples must have at least 2 sub-
registers
");
281
// Default allocation order always contains all
registers
.
366
// Copy all allocation orders, filter out foreign
registers
from the larger
406
// 1. All RC
registers
are also in this
[
all
...]
RegisterInfoEmitter.cpp
28
// runEnums - Print out enum values for all of the
registers
.
32
const std::vector<CodeGenRegister*> &
Registers
= Bank.getRegisters();
34
std::string Namespace =
Registers
[0]->TheDef->getValueAsString("Namespace");
50
for (unsigned i = 0, e =
Registers
.size(); i != e; ++i)
51
OS << " " <<
Registers
[i]->getName() << " = " <<
52
Registers
[i]->EnumValue << ",\n";
53
assert(
Registers
.size() ==
Registers
[
Registers
.size()-1]->EnumValue &&
55
OS << " NUM_TARGET_REGS \t// " <<
Registers
.size()+1 << "\n"
[
all
...]
CodeGenRegisters.h
47
// Get a map of sub-
registers
computed lazily.
48
// This includes unique entries for all sub-sub-
registers
.
52
assert(SubRegsComplete && "Must precompute sub-
registers
");
56
// Add sub-
registers
to OSet following a pre-order defined by the .td file.
59
// List of super-
registers
in topological order, small to large.
62
// Get the list of super-
registers
.
63
// This is only valid after computeDerivedInfo has visited all
registers
.
65
assert(SubRegsComplete && "Must precompute sub-
registers
");
90
// Allocation orders. Order[0] always contains all
registers
in Members.
143
// 1. All RC
registers
are also in this
[
all
...]
AsmWriterEmitter.cpp
464
const std::vector<CodeGenRegister*> &
Registers
) {
467
for (unsigned i = 0, e =
Registers
.size(); i != e; ++i) {
468
const CodeGenRegister &Reg = *
Registers
[i];
519
const std::vector<CodeGenRegister*> &
Registers
=
533
O << " assert(RegNo && RegNo < " << (
Registers
.size()+1)
539
emitRegisterNameString(O, AltNameIndices[i]->getName(),
Registers
);
541
emitRegisterNameString(O, "",
Registers
);
[
all
...]
AsmMatcherEmitter.cpp
175
/// For register classes, the records for all the
registers
in this class.
176
std::set<Record*>
Registers
;
196
//
Registers
classes are only related to
registers
classes, and only if
204
std::set_intersection(
Registers
.begin(),
Registers
.end(),
205
RHS.
Registers
.begin(), RHS.
Registers
.end(),
661
// Collect singleton
registers
, if used.
915
const std::vector<CodeGenRegister*> &
Registers
[
all
...]
/external/v8/tools/
profile.js
96
*
Registers
a library.
112
*
Registers
statically compiled code entry.
128
*
Registers
dynamic (JIT-compiled) code entry.
144
*
Registers
dynamic (JIT-compiled) code entry.
/external/llvm/lib/Target/ARM/AsmParser/
ARMAsmParser.cpp
276
SmallVector<unsigned, 8>
Registers
;
316
// A vector register list is a sequential list of 1 to 4
registers
.
402
Registers
= o.
Registers
;
484
return
Registers
;
779
// Thumb reg+reg addressing is simple. Just two
registers
, a base and
[
all
...]
/external/grub/netboot/
3c90x.c
54
enum
Registers
83
/** following are windowed
registers
**/
771
/** Program the MAC address into the station address
registers
**/
/external/zlib/contrib/masm686/
match.asm
122
; Saved
Registers
(actually pushed into place)
133
; Save
registers
that the compiler may be using
/external/openssl/crypto/bn/asm/
pa-risc2.s
37
; For the floating point
registers
39
; "caller save"
registers
: fr4-fr11, fr22-fr31
40
; "callee save"
registers
: fr12-fr21
41
; "special"
registers
: fr0-fr3 (status and exception
registers
)
43
; For the integer
registers
45
; "caller save"
registers
: r1,r19-r26
46
; "callee save"
registers
: r3-r18
918
;
Registers
to hold 64-bit values to manipulate. The "L" part
923
; using them because they are callee save
registers
[
all
...]
pa-risc2W.s
31
; For the floating point
registers
33
; "caller save"
registers
: fr4-fr11, fr22-fr31
34
; "callee save"
registers
: fr12-fr21
35
; "special"
registers
: fr0-fr3 (status and exception
registers
)
37
; For the integer
registers
39
; "caller save"
registers
: r1,r19-r26
40
; "callee save"
registers
: r3-r18
905
;
Registers
to hold 64-bit values to manipulate. The "L" part
910
; using them because they are callee save
registers
[
all
...]
Completed in 297 milliseconds