| /external/llvm/lib/Target/Sparc/ |
| SparcISelDAGToDAG.cpp | 147 case ISD::SDIV:
155 if (N->getOpcode() == ISD::SDIV) {
165 unsigned Opcode = N->getOpcode() == ISD::SDIV ? SP::SDIVrr : SP::UDIVrr;
|
| /external/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 189 ADD, SUB, MUL, SDIV, UDIV, SREM, UREM,
[all...] |
| /external/llvm/lib/Target/Alpha/ |
| AlphaISelLowering.cpp | 99 setOperationAction(ISD::SDIV , MVT::i64, Custom);
691 case ISD::SDIV:
695 return Op.getOpcode() == ISD::SDIV ? BuildSDIV(Op.getNode(), DAG, NULL)
702 case ISD::SDIV: opstr = "__divq"; break;
[all...] |
| /external/llvm/lib/Target/Blackfin/ |
| BlackfinISelLowering.cpp | 79 setOperationAction(ISD::SDIV, MVT::i16, Expand);
80 setOperationAction(ISD::SDIV, MVT::i32, Expand);
|
| /external/llvm/lib/Target/SystemZ/ |
| SystemZISelLowering.cpp | 98 setOperationAction(ISD::SDIV, MVT::i32, Expand);
100 setOperationAction(ISD::SDIV, MVT::i64, Expand);
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeVectorOps.cpp | 15 // ISD::SDIV of type v2i64 on x86-32. The type is legal (for example, addition
16 // on a v2i64 is legal), but ISD::SDIV isn't legal, so we have to unroll the
171 case ISD::SDIV:
|
| FastISel.cpp | 372 // Transform "sdiv exact X, 8" -> "sra X, 3".
373 if (ISDOpcode == ISD::SDIV && isa<BinaryOperator>(I) &&
897 case Instruction::SDiv:
898 return SelectBinaryOp(I, ISD::SDIV);
[all...] |
| LegalizeDAG.cpp | [all...] |
| LegalizeVectorTypes.cpp | 107 case ISD::SDIV:
480 case ISD::SDIV:
[all...] |
| DAGCombiner.cpp | [all...] |
| SelectionDAG.cpp | [all...] |
| LegalizeIntegerTypes.cpp | 108 case ISD::SDIV:
[all...] |
| TargetLowering.cpp | 645 case ISD::SDIV:
[all...] |
| SelectionDAGBuilder.cpp | [all...] |
| /external/llvm/lib/Target/CellSPU/ |
| SPUISelLowering.cpp | 182 setOperationAction(ISD::SDIV, MVT::i8, Expand);
188 setOperationAction(ISD::SDIV, MVT::i16, Expand);
194 setOperationAction(ISD::SDIV, MVT::i32, Expand);
200 setOperationAction(ISD::SDIV, MVT::i64, Expand);
206 setOperationAction(ISD::SDIV, MVT::i128, Expand);
422 setOperationAction(ISD::SDIV, VT, Expand);
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | 156 setOperationAction(ISD::SDIV, MVT::i8, Expand);
162 setOperationAction(ISD::SDIV, MVT::i16, Expand);
[all...] |
| /external/llvm/lib/Target/MBlaze/ |
| MBlazeISelLowering.cpp | 122 setOperationAction(ISD::SDIV, MVT::i32, Expand);
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelDAGToDAG.cpp | [all...] |
| PPCISelLowering.cpp | 319 setOperationAction(ISD::SDIV, VT, Expand);
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | 138 setOperationAction(ISD::SDIV, MVT::i32, Expand);
142 setOperationAction(ISD::SDIV, MVT::i64, Expand);
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | 151 setOperationAction(ISD::SDIV, VT.getSimpleVT(), Expand);
494 setOperationAction(ISD::SDIV, MVT::v4i16, Custom);
495 setOperationAction(ISD::SDIV, MVT::v8i8, Custom);
588 setOperationAction(ISD::SDIV, MVT::i32, Expand);
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | 355 setOperationAction(ISD::SDIV, VT, Expand);
693 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand);
[all...] |
