| /external/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 684 /// SEXTLOAD loads the integer operand and sign extends it to a larger
693 SEXTLOAD,
[all...] |
| SelectionDAGNodes.h | [all...] |
| /external/llvm/lib/Target/Alpha/ |
| AlphaISelLowering.cpp | 67 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
68 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
69 setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Expand);
550 SDValue Offset = DAG.getExtLoad(ISD::SEXTLOAD, dl, MVT::i64, Base.getValue(1),
717 Result = DAG.getExtLoad(ISD::SEXTLOAD, dl, MVT::i64, Chain, DataPtr,
740 Val = DAG.getExtLoad(ISD::SEXTLOAD, dl, MVT::i64, Result,
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZISelLowering.cpp | 63 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
67 setLoadExtAction(ISD::SEXTLOAD, MVT::f32, Expand);
71 setLoadExtAction(ISD::SEXTLOAD, MVT::f64, Expand);
[all...] |
| /external/llvm/lib/Target/MBlaze/ |
| MBlazeISelLowering.cpp | 94 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
97 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
98 setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Expand);
[all...] |
| /external/llvm/lib/Target/PTX/ |
| PTXISelLowering.cpp | 57 setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Expand);
|
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | 90 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
92 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
93 setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Expand);
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| DAGCombiner.cpp | [all...] |
| LegalizeDAG.cpp | [all...] |
| LegalizeIntegerTypes.cpp | [all...] |
| SelectionDAG.cpp | [all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | 278 ISD::LoadExtType LoadOp = ISD::SEXTLOAD;
700 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
[all...] |
| /external/llvm/lib/Target/Blackfin/ |
| BlackfinISelLowering.cpp | 58 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
|
| /external/llvm/lib/Target/CellSPU/ |
| SPUISelLowering.cpp | 117 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
143 setLoadExtAction(ISD::SEXTLOAD, VT, Custom);
735 if (ExtType == ISD::SEXTLOAD) {
[all...] |
| /external/llvm/lib/Transforms/Scalar/ |
| CodeGenPrepare.cpp | [all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreISelLowering.cpp | 130 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
132 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelDAGToDAG.cpp | [all...] |
| PPCISelLowering.cpp | 85 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
86 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
87 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelDAGToDAG.cpp | [all...] |
| ARMISelLowering.cpp | 128 setLoadExtAction(ISD::SEXTLOAD, VT.getSimpleVT(), Expand);
532 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | 112 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | 233 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
[all...] |
