| /external/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 375 // SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to
380 SIGN_EXTEND_INREG,
[all...] |
| /external/llvm/lib/Target/PTX/ |
| PTXISelLowering.cpp | 67 // sign_extend_inreg => sign_extend
69 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeIntegerTypes.cpp | 71 case ISD::SIGN_EXTEND_INREG:
397 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res,
462 SDValue Ofl = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res,
535 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(),
667 SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, Mul.getValueType(),
[all...] |
| LegalizeVectorOps.cpp | 218 case ISD::SIGN_EXTEND_INREG:
|
| DAGCombiner.cpp | 724 if (!TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, PVT))
736 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NewOp.getValueType(), NewOp,
[all...] |
| LegalizeTypes.h | 201 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Op.getValueType(), Op,
[all...] |
| LegalizeDAG.cpp | [all...] |
| LegalizeVectorTypes.cpp | 61 case ISD::SIGN_EXTEND_INREG: R = ScalarizeVecRes_InregOp(N); break;
431 case ISD::SIGN_EXTEND_INREG: SplitVecRes_InregOp(N, Lo, Hi); break;
[all...] |
| SelectionDAG.cpp | [all...] |
| TargetLowering.cpp | [all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | 710 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
711 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand);
712 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | 139 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
[all...] |
| /external/llvm/lib/Target/Blackfin/ |
| BlackfinISelLowering.cpp | 110 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
|
| /external/llvm/lib/Target/SystemZ/ |
| SystemZISelLowering.cpp | 107 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
[all...] |
| /external/llvm/lib/Target/MBlaze/ |
| MBlazeISelLowering.cpp | 163 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | 153 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
207 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
208 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
[all...] |
| /external/llvm/lib/Target/Alpha/ |
| AlphaISelLowering.cpp | 78 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | 372 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
373 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
374 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
375 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
735 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,Expand);
[all...] |
| /external/llvm/lib/Target/CellSPU/ |
| SPUISelLowering.cpp | 357 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | 664 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
665 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
667 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 189 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
[all...] |
