| /external/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 372 SINT_TO_FP,
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeVectorOps.cpp | 224 case ISD::SINT_TO_FP:
423 // Make sure that the SINT_TO_FP and SRL instructions are available.
424 if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, VT) ||
450 SDValue fHI = DAG.getNode(ISD::SINT_TO_FP, DL, Op.getValueType(), HI);
452 SDValue fLO = DAG.getNode(ISD::SINT_TO_FP, DL, Op.getValueType(), LO);
|
| LegalizeDAG.cpp | [all...] |
| LegalizeFloatTypes.cpp | 96 case ISD::SINT_TO_FP:
540 bool Signed = N->getOpcode() == ISD::SINT_TO_FP;
[all...] |
| LegalizeVectorTypes.cpp | 90 case ISD::SINT_TO_FP:
467 case ISD::SINT_TO_FP:
[all...] |
| FastISel.cpp | 196 Reg = FastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP,
[all...] |
| LegalizeIntegerTypes.cpp | [all...] |
| DAGCombiner.cpp | [all...] |
| SelectionDAGBuilder.cpp | [all...] |
| SelectionDAG.cpp | [all...] |
| /external/llvm/lib/Target/CellSPU/ |
| SPUISelLowering.cpp | 342 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
343 setOperationAction(ISD::SINT_TO_FP, MVT::i16, Promote);
344 setOperationAction(ISD::SINT_TO_FP, MVT::i8, Promote);
348 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
384 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
[all...] |
| /external/llvm/lib/Target/Alpha/ |
| AlphaISelLowering.cpp | 84 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
619 case ISD::SINT_TO_FP: {
621 "Unhandled SINT_TO_FP type in custom expander!");
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | 722 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | 113 setOperationAction(ISD::SINT_TO_FP, VT.getSimpleVT(), Expand);
500 // Neon does not have single instruction SINT_TO_FP and UINT_TO_FP with
502 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Custom);
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | 251 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
269 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
271 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
272 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
277 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
279 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
281 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
282 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
285 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote)
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 180 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
257 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
266 //setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
386 setTargetDAGCombine(ISD::SINT_TO_FP);
[all...] |
