| /external/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 189 ADD, SUB, MUL, SDIV, UDIV, SREM, UREM,
[all...] |
| /external/llvm/lib/Target/Blackfin/ |
| BlackfinISelLowering.cpp | 83 setOperationAction(ISD::SREM, MVT::i16, Expand);
84 setOperationAction(ISD::SREM, MVT::i32, Expand);
|
| /external/llvm/lib/Target/SystemZ/ |
| SystemZISelLowering.cpp | 102 setOperationAction(ISD::SREM, MVT::i32, Expand);
104 setOperationAction(ISD::SREM, MVT::i64, Expand);
[all...] |
| /external/llvm/lib/Target/Alpha/ |
| AlphaISelLowering.cpp | 97 setOperationAction(ISD::SREM , MVT::i64, Custom);
679 case ISD::SREM:
700 case ISD::SREM: opstr = "__remq"; break;
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeVectorOps.cpp | 173 case ISD::SREM:
|
| SelectionDAGBuilder.h | 485 void visitSRem(const User &I) { visitBinary(I, ISD::SREM); }
|
| LegalizeVectorTypes.cpp | 108 case ISD::SREM:
491 case ISD::SREM:
[all...] |
| SelectionDAG.cpp | [all...] |
| LegalizeDAG.cpp | [all...] |
| FastISel.cpp | 903 case Instruction::SRem:
904 return SelectBinaryOp(I, ISD::SREM);
[all...] |
| LegalizeIntegerTypes.cpp | 109 case ISD::SREM: Res = PromoteIntRes_SDIV(N); break;
[all...] |
| DAGCombiner.cpp | [all...] |
| TargetLowering.cpp | 647 case ISD::SREM:
[all...] |
| /external/llvm/lib/Target/CellSPU/ |
| SPUISelLowering.cpp | 180 setOperationAction(ISD::SREM, MVT::i8, Expand);
186 setOperationAction(ISD::SREM, MVT::i16, Expand);
192 setOperationAction(ISD::SREM, MVT::i32, Expand);
198 setOperationAction(ISD::SREM, MVT::i64, Expand);
204 setOperationAction(ISD::SREM, MVT::i128, Expand);
423 setOperationAction(ISD::SREM, VT, Expand);
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | 158 setOperationAction(ISD::SREM, MVT::i8, Expand);
164 setOperationAction(ISD::SREM, MVT::i16, Expand);
[all...] |
| /external/llvm/lib/Target/MBlaze/ |
| MBlazeISelLowering.cpp | 102 setOperationAction(ISD::SREM, MVT::i32, Expand);
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | 716 setOperationAction(ISD::SREM, MVT::i32, Expand);
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | 139 setOperationAction(ISD::SREM, MVT::i32, Expand);
143 setOperationAction(ISD::SREM, MVT::i64, Expand);
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 107 // PowerPC has no SREM/UREM instructions
108 setOperationAction(ISD::SREM, MVT::i32, Expand);
110 setOperationAction(ISD::SREM, MVT::i64, Expand);
113 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
320 setOperationAction(ISD::SREM, VT, Expand);
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | 154 setOperationAction(ISD::SREM, VT.getSimpleVT(), Expand);
591 setOperationAction(ISD::SREM, MVT::i32, Expand);
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | 357 setOperationAction(ISD::SREM, VT, Expand);
696 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand);
[all...] |
