| /external/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 217 ADDE, SUBE,
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsISelDAGToDAG.cpp | 209 case ISD::SUBE:
214 (Opc == ISD::SUBC || Opc == ISD::SUBE)) &&
|
| MipsISelLowering.cpp | 218 setTargetDAGCombine(ISD::SUBE);
319 // (addc Lo0, multLo), (sube Hi0, multHi),
381 // replace uses of sube and subc here
646 case ISD::SUBE:
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.h | 77 SUBE, // Sub using carry
|
| ARMISelLowering.cpp | 571 setOperationAction(ISD::SUBE, MVT::i32, Custom);
[all...] |
| /external/llvm/lib/Target/Blackfin/ |
| BlackfinISelLowering.cpp | 99 setOperationAction(ISD::SUBE, MVT::i32, Custom);
422 // Expansion of ADDE / SUBE. This is a bit involved since blackfin doesn't have
472 case ISD::SUBE: return LowerADDE(Op, DAG);
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeIntegerTypes.cpp | [all...] |
| SelectionDAG.cpp | [all...] |
| /external/llvm/lib/Target/Alpha/ |
| AlphaISelLowering.cpp | 105 setOperationAction(ISD::SUBE , MVT::i64, Expand);
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreISelLowering.cpp | 92 setOperationAction(ISD::SUBE, MVT::i32, Expand);
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | 364 setOperationAction(ISD::SUBE, VT, Custom);
[all...] |
