| /external/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 189 ADD, SUB, MUL, SDIV, UDIV, SREM, UREM,
[all...] |
| /external/llvm/lib/Target/Alpha/ |
| AlphaISelLowering.cpp | 98 setOperationAction(ISD::UREM , MVT::i64, Custom);
678 case ISD::UREM:
683 SDValue Tmp1 = Op.getNode()->getOpcode() == ISD::UREM ?
699 case ISD::UREM: opstr = "__remqu"; break;
[all...] |
| /external/llvm/lib/Target/Blackfin/ |
| BlackfinISelLowering.cpp | 89 setOperationAction(ISD::UREM, MVT::i16, Expand);
90 setOperationAction(ISD::UREM, MVT::i32, Expand);
|
| /external/llvm/lib/Target/SystemZ/ |
| SystemZISelLowering.cpp | 103 setOperationAction(ISD::UREM, MVT::i32, Expand);
105 setOperationAction(ISD::UREM, MVT::i64, Expand);
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeVectorOps.cpp | 174 case ISD::UREM:
|
| SelectionDAGBuilder.h | 484 void visitURem(const User &I) { visitBinary(I, ISD::UREM); }
|
| LegalizeVectorTypes.cpp | 111 case ISD::UREM:
490 case ISD::UREM:
[all...] |
| SelectionDAG.cpp | [all...] |
| FastISel.cpp | 905 case Instruction::URem:
906 return SelectBinaryOp(I, ISD::UREM);
[all...] |
| DAGCombiner.cpp | [all...] |
| LegalizeDAG.cpp | [all...] |
| LegalizeIntegerTypes.cpp | 112 case ISD::UREM: Res = PromoteIntRes_UDIV(N); break;
[all...] |
| TargetLowering.cpp | 648 case ISD::UREM:
[all...] |
| /external/llvm/lib/Target/CellSPU/ |
| SPUISelLowering.cpp | 181 setOperationAction(ISD::UREM, MVT::i8, Expand);
187 setOperationAction(ISD::UREM, MVT::i16, Expand);
193 setOperationAction(ISD::UREM, MVT::i32, Expand);
199 setOperationAction(ISD::UREM, MVT::i64, Expand);
205 setOperationAction(ISD::UREM, MVT::i128, Expand);
425 setOperationAction(ISD::UREM, VT, Expand);
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | 155 setOperationAction(ISD::UREM, MVT::i8, Expand);
161 setOperationAction(ISD::UREM, MVT::i16, Expand);
[all...] |
| /external/llvm/lib/Target/MBlaze/ |
| MBlazeISelLowering.cpp | 101 setOperationAction(ISD::UREM, MVT::i32, Expand);
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | 715 setOperationAction(ISD::UREM, MVT::i32, Expand);
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | 141 setOperationAction(ISD::UREM, MVT::i32, Expand);
145 setOperationAction(ISD::UREM, MVT::i64, Expand);
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 107 // PowerPC has no SREM/UREM instructions
109 setOperationAction(ISD::UREM, MVT::i32, Expand);
111 setOperationAction(ISD::UREM, MVT::i64, Expand);
113 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
322 setOperationAction(ISD::UREM, VT, Expand);
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | 155 setOperationAction(ISD::UREM, VT.getSimpleVT(), Expand);
592 setOperationAction(ISD::UREM, MVT::i32, Expand);
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | 358 setOperationAction(ISD::UREM, VT, Expand);
697 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand);
[all...] |
